Semiconductor device and manufacturing method thereof

ABSTRACT

Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2008-101242 filed onApr. 9, 2008 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing technology thereof. In particular, the invention pertainsto a semiconductor device obtained by forming a trench gate type powerMISFET (Metal Insulator Semiconductor Field Effect Transistor) and aSchottky barrier diode over one semiconductor substrate and a technologyeffective when applied to the manufacture of the semiconductor device.

Japanese Patent No. 2997247 (Patent Document 1) describes a technologyof forming a trench gate type power MISFET, a clamping diode, and aSchottky diode over one semiconductor substrate. An object of thistechnology is to set the avalanche breakdown voltage of the clampingdiode lower than the avalanche breakdown voltage of a body diodeincorporated in the power MISFET, thereby improving the avalanchecapability of the entire semiconductor device.

To fulfill the object, a heavily-doped epitaxial region (Nepi1) isformed over the semiconductor substrate (N+ substrate) and alightly-doped epitaxial region (Nepi2) is formed over this heavily-dopedepitaxial region (Nepi1) in Patent Document 1. A boundary between theheavily-doped epitaxial region (Nepi1) and the lightly-doped epitaxialregion (Nepi2) is formed at a position deeper than the trench of thepower MISFET. In a clamping diode formation region, a deep P+ layer(deep protective P+ diffusion portion 38) is formed and this deep P+layer is brought into contact with the heavily-doped epitaxial region(Nepi1) to form a clamping diode having an avalanche breakdown voltagelower than the avalanche breakdown voltage of the body diode of thepower MISFET.

In a Schottky barrier diode formation region, on the other hand, theSchottky barrier diode is made of the lightly-doped epitaxial region(Nepi2) and a metal layer (Schottky metal layer 41) formed over thislightly-doped epitaxial region (Nepi2). Also in this Schottky barrierdiode formation region, a boundary between the lightly-doped epitaxialregion (Nepi2) and the highly-doped epitaxial region (Nepi1) is formedat a position deeper than the trench of the power MISFET. Although theSchottky barrier diode is formed between trenches, the lightly-dopedepitaxial region (Nepi2) formed between the trenches is fully depletedby decreasing the distance between these trenches. This improves theavalanche breakdown voltage of the Schottky barrier diode.

U.S. Pat. No. 6,351,018 (Patent Document 2) describes a technology offorming a trench-gate type power MISFET and a Schottky barrier diodeover one semiconductor substrate. An object of the technology describedin Patent Document 2 is to make an avalanche breakdown voltage of theSchottky barrier diode higher than the avalanche breakdown voltage ofthe power MISFET. In order to achieve this object, the distance betweentrenches having the Schottky barrier diode sandwiched therebetweennarrower than the distance between the trenches having therebetweencells in which the power MISFET has been formed. Narrowing of thedistance between trenches sandwiching the Schottky barrier diodetherebetween is effective for reducing the field intensity on thesurface of an epitaxial region in which a Schottky junction is formed(RESURF effect). This leads to improvement in avalanche capability ofthe Schottky barrier and as a result, enables to make the avalanchebreakdown voltage of the Schottky barrier diode higher than theavalanche breakdown voltage of the power MISFET.

Japanese Patent Laid-Open No. 2003-133557 (Patent Document 3) describesa technology of forming a trench gate type power MISFET and a Schottkybarrier diode over one semiconductor substrate. According to thetechnology described in this Patent Document 3, the avalanche breakdownvoltage of the Schottky barrier diode is made higher than the avalanchebreakdown voltage of the power MISFET. Described specifically, an n⁻type semiconductor layer (1b) is formed over a semiconductor substrate.In a Schottky barrier diode formation region, an electrode (14) isformed over this n⁻ type semiconductor layer (1b) to form a Schottkybarrier diode. In the power MISFET formation region, on the other hand,the n⁻ type semiconductor layer (1b) and a p⁻ type semiconductor region(4) which is a channel region are not brought into contact, but an ntype semiconductor region (17) is formed so as to be brought into directcontact with the p⁻ type semiconductor region (4) which is a channelregion. This n type semiconductor region (17) is formed so as to have adoping concentration higher than that of the n⁻ type semiconductor layer(1b). By employing such a configuration, the avalanche breakdown voltageof the power MISFET is determined by a pn junction between the n typesemiconductor region (17) and the p⁻ type semiconductor region (4) whichis a channel region. Since the doping concentration of the n typesemiconductor region (17) forming a pn junction with the channel region(p⁻ type semiconductor region (4)) of the power MISFET is higher thanthat of the n⁻ type semiconductor layer (1b) configuring the Schottkybarrier diode, the avalanche breakdown voltage of the Schottky barrierdiode can be made higher than the avalanche breakdown voltage of thepower MISFET.

SUMMARY OF THE INVENTION

For example, electronic appliances such as personal computers use aDC/DC converter for converting the voltage of a DC power supply from onevoltage level to another one. For this DC/DC converter, a power MISFETis used as a switching element, and a Schottky barrier diode is usedfrom the standpoint of reducing a loss of circuit. For DC/DC converters,there is, for example, a semiconductor device having a power MISFET anda Schottky barrier diode on one semiconductor substrate. In such asemiconductor device, an epitaxial layer is formed on the semiconductorsubstrate, followed by the formation of the power MISFETE and theSchottky barrier diode on the epitaxial layer. Described specifically, ametal film is formed on the epitaxial layer in a first region (Schottkybarrier diode formation region) of the semiconductor substrate and by aSchottky junction obtained by the contact between the epitaxial layerand the metal film, a Schottky barrier diode is formed. In a secondregion (power MISFET formation region) of the semiconductor substrate,on the other hand, a trench is formed in the epitaxial layer and thetrench is filled with a conductor film to form a gate electrode.Further, a channel region is formed in the epitaxial layer and a sourceregion is formed above this channel region. In the power MISFET havingsuch a configuration, when a predetermined voltage is applied to thegate electrode, an inversion layer is formed in the channel region onthe side surface of the trench in which the gate electrode has beenformed and this inversion layer contributes to conduction between thesource region and the epitaxial layer. In short, electrons from thesource region pass through the inversion layer and the epitaxial layerand reach the semiconductor substrate and then, reach a drain electrodeformed on the backside of the semiconductor substrate, whereby the powerMISFET is turned ON.

From the above description, it is apparent that the epitaxial layerfunctions as a current-flowing drift layer from the viewpoint of thepower MISFET, while it functions as a semiconductor layer forming aSchottky junction from the viewpoint of the Schottky barrier diode.Since an electric current of the power MISFET passes through theepitaxial layer, it is therefore desired to have low resistance (lowon-resistance).

The power MISFET and the Schottky barrier diode have been formed on onesemiconductor substrate and both of these elements have an avalanchebreakdown voltage. For example, the avalanche breakdown voltage of thepower MISFET is determined by a pn junction between the epitaxial layerand the channel region. The avalanche breakdown voltage of the Schottkybarrier diode is, on the other hand, determined by the dopingconcentration of the epitaxial layer which is a semiconductor layerforming a Schottky junction. From the standpoint of obtaining asemiconductor device having improved reliability, the avalanchebreakdown voltage of the Schottky barrier diode is desirably higher thanthe avalanche breakdown voltage of the power MISFET.

For example, when the avalanche breakdown voltage of the power MISFET islower than the avalanche breakdown voltage of the Schottky barrierdiode, breakdown occurs at the pn junction (between epitaxial layer andchannel formation region) in the bulk, making it difficult to causecharacteristics variations of the semiconductor device. On the otherhand, when the avalanche breakdown voltage of the Schottky barrier diodeis lower than the avalanche breakdown voltage of the power MISFET,characteristics variations of the semiconductor device are likely tooccur due to carriers generated by avalanche breakdown which hasoccurred on the surface of the epitaxial layer because Schottky junctionis present at the surface of the epitaxial layer. This means thatcharacteristics variations have a greater influence on the entiresemiconductor device when the avalanche breakdown occurs on the surfaceof the epitaxial layer than when the avalanche breakdown occurs insidethe epitaxial layer, leading to deterioration in the reliability of thesemiconductor device. It is therefore necessary to make the avalanchebreakdown voltage of the Schottky barrier diode higher than theavalanche breakdown voltage of the power MISFET.

Improvement of avalanche capability of the Schottky barrier diode can beachieved by reducing the doping concentration of the epitaxial layerforming a Schottky junction. As described above, however, the epitaxiallayer functions as a drift layer of the power MISFET so that theon-resistance of the power MISFET should be reduced. From the viewpointof reducing the on-resistance of the power MISFET, the dopingconcentration of the epitaxial layer should be raised. This suggeststhat the improvement of avalanche capability of the Schottky barrierdiode and reduction in the on-resistance of the power MISFET is in atrade-off relationship.

An object of the invention is to provide a technology, in asemiconductor device having a power MISFET and a Schottky barrier diodeon one semiconductor substrate, of making the avalanche breakdownvoltage of the Schottky barrier diode higher than the avalanchebreakdown voltage of the power MISFET, while suppressing a drasticincrease in the on-resistance of the power MISFET.

The above-described and the other objects, and novel features of theinvention will be apparent from the description herein and accompanyingdrawings.

Of the inventions disclosed in the present application, summary of therepresentative ones will next be described briefly.

A semiconductor device according to a representative embodiment has afirst region in which a Schottky barrier diode has been formed and asecond region in which a power MISFET has been formed. In the firstregion, (a1) a semiconductor substrate of a first conductivity typehaving an upper surface and a lower surface on a side opposite theretoand (a2) a first semiconductor layer of the first conductivity typeformed over the upper surface of the semiconductor substrate are formed.Moreover, (a3) a second semiconductor layer of the first conductivitytype formed over the first semiconductor layer, (a4) a first metal filmformed over the second semiconductor layer, and (a5) a second metal filmformed over the lower surface of the semiconductor substrate are formed.The second semiconductor layer forms a Schottky junction with the firstmetal film.

In the second region, (b1) the semiconductor substrate, (b2) the firstsemiconductor layer formed over the semiconductor substrate, and (b3) achannel region formed in the first semiconductor layer and having asecond conductivity type opposite to the first conductivity type areformed. Moreover, (b4) a trench penetrating the channel region andreaching the first semiconductor layer; (b5) a gate insulating filmformed over an inner wall of the trench, and (b6) a gate electrodeformed over the gate insulating film, and filled in the trench areformed. Further, (b7) a source region of the first conductivity typecontiguous to the trench and formed over the channel region, (b8) thefirst metal film formed over the source region and electrically coupledto the source region, and (b9) the second metal film formed over thelower surface of the semiconductor substrate are formed.

The first metal film functions as an anode electrode of the Schottkybarrier diode in the first region and as a source electrode of the powerMISFET in the second region, while the second metal film functions as acathode electrode of the Schottky barrier diode in the first region andas a drain electrode of the power MISFET in the second region.

The doping concentration of the second semiconductor layer is lower thanthat of the first semiconductor layer, and the boundary between thefirst semiconductor layer and the second semiconductor layer is formedin a region as deep as the bottom portion of the trench or shallowerthan the bottom portion of the trench.

A manufacturing method of a semiconductor device according to arepresentative embodiment has the step of (a) preparing a multilayersubstrate having a semiconductor substrate of a first conductivity type,a first semiconductor layer of the first conductivity type formed overthe semiconductor substrate, and a second semiconductor layer of thefirst conductivity type formed over the first semiconductor layer andhaving a doping concentration lower than that of the first semiconductorlayer. It has further the steps of (b) forming a trench in a secondregion of the multilayer substrate in which a power MISFET is to beformed, (c) forming a gate insulating film over an inner wall of thetrench, and (d) forming a gate electrode over the gate insulating filmso as to fill the trench. It has still further steps of (e) forming achannel region of a second conductivity type opposite to the firstconductivity type in the second region of the multilayer substrate, and(f) forming, in the second region of the multilayer substrate, a sourceregion contiguous to the trench and composed of a semiconductor regionof the first conductivity type. It has then the steps of (g) forming afirst metal film which comes in contact with the source region in thesecond region of the multilayer substrate and comes in contact with thesecond semiconductor layer to form a Schottky junction in a first regionof the multilayer substrate forming a Schottky barrier diode and (h)forming a second metal film over the lower surface of the semiconductorsubstrate included in the multilayer substrate.

At this time, the first metal film serves as a source electrode of thepower MISFET in the second region, and an anode electrode of theSchottky barrier diode in the first region, while the second metal filmserves as a drain electrode of the power MISFET in the second region,and a cathode electrode of the Schottky barrier diode in the firstregion.

After completion of the power MISFET and the Schottky barrier diode, theboundary between the first semiconductor layer and the secondsemiconductor layer is present in a region as deep as or shallower thanthe bottom portion of the trench.

Of the inventions disclosed by the present application, advantagesavailable by the representative inventions will hereinafter be describedbriefly.

According to the representative embodiments of the invention, in asemiconductor device having a power MISFET and a Schottky barrier diodeon one semiconductor substrate, the avalanche breakdown voltage of theSchottky barrier diode can be made higher than the avalanche breakdownvoltage of the power MISFET and a drastic increase in the on-resistanceof the power MISFET can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a general synchronous rectifier typeDC/DC converter using a power MISFET;

FIG. 2 is a timing chart of the power MISFET Q1 for main switch and thepower MISFET Q2 for synchronous rectification, each illustrated in FIG.1;

FIG. 3 is a plan view illustrating an upper surface of a semiconductorchip having therein a power MISFET and a Schottky barrier diode;

FIG. 4 is a plan view illustrating another method of adjusting the areaof a Schottky barrier diode;

FIG. 5 is an enlarged plan view of a partial region of FIG. 3;

FIG. 6 is a cross-sectional view taken along a line X-X of FIG. 5;

FIG. 7 is a graph showing a change in the doping concentration along theline D1-D1 of FIG. 6;

FIG. 8 is a graph showing the relationship between a dopingconcentration of the surface of an epitaxial layer (second semiconductorlayer) and an avalanche breakdown voltage;

FIG. 9 is a graph showing a change in doping concentration along a lineD2-D2 of FIG. 6;

FIG. 10 is a graph, in the first simulation, showing the relationshipbetween a depth from the surface of a second epitaxial layer and adoping concentration after formation of a first epitaxial layer and thesecond epitaxial layer over the semiconductor substrate;

FIG. 11 is a graph showing the relationship between a depth from thesurface of the second epitaxial layer and a doping concentration aftercompletion of a semiconductor device having a power MISFET and aSchottky barrier diode SBD (first simulation);

FIG. 12 is a graph showing the relationship between a depth from thesurface of the second epitaxial layer and a doping concentration in thepower MISFET formation region (first simulation);

FIG. 13 is a graph showing the relationship between a thickness of thesecond epitaxial layer and an avalanche breakdown voltage of theSchottky barrier diode SBD and between a thickness of the secondepitaxial layer and an avalanche breakdown voltage of the power MISFET;

FIG. 14 is a graph, in the first simulation, showing the relationshipbetween a thickness of the second epitaxial layer and a relativeon-resistance of the power MISFET;

FIG. 15 is a graph, in the second simulation, showing the relationshipbetween a depth from the surface of the second epitaxial layer and adoping concentration after formation of the first epitaxial layer andthe second epitaxial layer over the semiconductor substrate;

FIG. 16 is a graph showing the relationship between a depth from thesurface of the second epitaxial layer and a doping concentration aftercompletion of the semiconductor device having a power MISFET and aSchottky barrier diode SBD (second simulation);

FIG. 17 is a graph showing a depth from the surface of the secondepitaxial layer and a doping concentration in the power MISFET formationregion (second simulation);

FIG. 18 is a graph showing the relationship between a thickness of thesecond epitaxial layer and an avalanche breakdown voltage of theSchottky barrier diode SBD and a thickness of the second epitaxial layerand an avalanche breakdown voltage of the power MISFET;

FIG. 19 is a graph, in the second simulation, showing the relationshipbetween a thickness of the second epitaxial layer and a relativeon-resistance of the power MISFET;

FIG. 20 is a graph showing the relationship between a depth from thesurface of the second epitaxial layer and a field intensity;

FIG. 21 is a graph showing the relationship between a forward voltageand a forward current in a structure in which a Schottky barrier diodeand a power MISFET are formed over one semiconductor substrate and theyare coupled to each other in parallel;

FIG. 22 is a graph showing the relationship between a breakdown voltage(reverse voltage) and a leakage current;

FIG. 23 illustrates a band structure of a metal film and a semiconductorlayer forming a Schottky junction;

FIG. 24 is a cross-sectional view illustrating a manufacturing step of asemiconductor device according to Embodiment 1 of the present invention;

FIG. 25 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 24;

FIG. 26 is a cross-sectional view illustrating another method forforming a multilayer substrate;

FIG. 27 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 26;

FIG. 28 is a cross-sectional view illustrating a further method forforming a multilayer substrate;

FIG. 29 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 28;

FIG. 30 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 29;

FIG. 31 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 30;

FIG. 32 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 31;

FIG. 33 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 32;

FIG. 34 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 33;

FIG. 35 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 34;

FIG. 36 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 35;

FIG. 37 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 36;

FIG. 38 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 37;

FIG. 39 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 38;

FIG. 40 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 39;

FIG. 41 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 40;

FIG. 42 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 41;

FIG. 43 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 42;

FIG. 44 is a cross-sectional view illustrating a manufacturing step ofthe semiconductor device following that of FIG. 43;

FIG. 45 is a cross-sectional view illustrating a semiconductor deviceaccording to Embodiment 2;

FIG. 46 is a graph showing the relationship between a reverse biasvoltage VR to be applied to the Schottky barrier diode and a leakagecurrent flowing through the Schottky barrier diode SBD; and

FIG. 47 is a cross-sectional view illustrating the configuration of asemiconductor device which is a modification example of Embodiment 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the below-described embodiments, a description will be made afterdivided in plural sections or in plural embodiments if necessary forconvenience's sake. These plural sections or embodiments are notindependent each other, but in a relation such that one is amodification example, details or complementary description of a part orwhole of the other one unless otherwise specifically indicated.

In the below-described embodiments, when a reference is made to thenumber of elements (including the number, value, amount, and range), thenumber of elements is not limited to a specific number but can begreater than or less than the specific number unless otherwisespecifically indicated or principally apparent that the number islimited to the specific number.

Moreover in the below-described embodiments, it is needless to say thatthe constituent elements (including element steps) are not alwaysessential unless otherwise specifically indicated or principallyapparent that they are essential.

Similarly, in the below-described embodiments, when a reference is madeto the shape or positional relationship of the constituent elements,that substantially analogous or similar to it is also embraced unlessotherwise specifically indicated or obviously different in principle.This also applies to the above-described value and range.

In all the drawings for describing the below-described embodiments,members having like function will be identified by like referencenumerals and overlapping descriptions will be omitted. In the drawingsused in these embodiments, even a plan view is sometimes hatched tofacilitate understanding of the drawing.

Embodiment 1

In this embodiment 1, an application example of a technology of forminga power MISFET and a Schottky barrier diode over one semiconductor chipto the present invention will be described.

FIG. 1 is a circuit diagram of a general synchronous rectifier typeDC/DC converter using a power MISFET and FIG. 2 is a timing chart of apower MISFET Q1 for main switch and a power MISFET Q2 for synchronousrectification, each MISFET illustrated in FIG. 1. In FIG. 1, the Q1 is apower MISFET for main switch, the Q2 is a power MISFET for synchronousrectification, BD1 and BD2 are body diodes, and SBD is a Schottkybarrier diode. In addition, L means inductance and C means a capacitorelement. The body diode BD1 and the body diode BD2 are incorporated inthe power MISFET Q1 for main switch and the power MISFET Q2 forsynchronous rectification, respectively and they are coupled to eachother in parallel. The Schottky barrier diode SBD is coupled in parallelto the power MISFET Q2 for synchronous rectification.

The main-switch MISFET Q1 functions as a switching element, while thesynchronous-rectification power MISFET Q2 functions as an element forsynchronous rectification. When the main-switch power MISFET Q1 isturned on, electric current flows from the side of an input voltage Vinto the side of inductance L and the capacitor element C through themain-switch power MISFET Q1, as shown in FIG. 1 (current flowing duringperiod A). Then, when the main-switch power MISFET Q1 is turned off andthe synchronous-rectification power MISFET Q2 is turned on, theinductance L acts to permit electric current to flow in a direction soas not to cause current reduction. Electric current therefore flows fromthe synchronous-rectification power MISFET Q2 to the side of theinductance L and the capacitor element C, as shown in FIG. 1 (currentflowing during period B). By repeating these operations, a predeterminedoutput voltage Vout is output from the input voltage.

The DC/DC converter is used, for example, in personal computers (PCs).The trends in the operating voltage of CPUs integrated in personalcomputers have been toward lower voltage and larger current. Inparticular, in the case of power supplies for notebook PCs, sizereduction is considered important so that the operating frequency alsotends to be high. As the trends toward lower voltage, larger current,and higher frequency progress in this way, it is necessary to extremelynarrow the switching pulse width of the main-switch power MISFET in theon/off operation. Conversely, the on time of thesynchronous-rectification power MISFET becomes about 90% of one period.Such usage requires a low switching loss for the main-switch powerMISFET and a low on-resistance for the synchronous rectification powerMISFET.

In the synchronous rectifier type DC/DC converter illustrated in FIG. 1,the main-switch power MISFET Q1 and the synchronous-rectification powerMISFET Q2 need to be alternately turned on and off. In order to preventthe through-current because of the simultaneous turn-on of themain-switch power MISFET Q1 and the synchronous-rectification powerMISFET Q2, a period called “dead time,” in which both MISFETs are turnedoff, is provided as illustrated in FIG. 2. The current during thatperiod flows in the direction indicated as the current flowing duringperiod B in FIG. 1. Described specifically, by turning off thesynchronous-rectification power MISFET Q2, the current flowing duringthe period B is blocked so that the current flows so as to keep thecurrent flowing during the period of B by the inductance L. During thisperiod, the current flows through the body diode BD2 integrated in thesynchronous-rectification power MISFET Q2, so a drop of forward voltage(VF) becomes large, about 0.8V. In view of this, the Schottky barrierdiode SBD which has a smaller voltage than the forward voltage (VF) ofthe body diode BD2 is coupled in parallel to thesynchronous-rectification power MISFET Q2 to reduce the circuit loss. Inother words, the circuit loss during the dead time is reduced by makinguse of a small drop in forward voltage (VF) of the Schottky barrierdiode SBD.

Accordingly, the use of a Schottky barrier diode is necessary from theviewpoint of reducing the circuit loss. In view of this, there is asemiconductor device in which a semiconductor chip having a power MISFETand a semiconductor chip having a Schottky barrier diode areencapsulated in a single package. In this semiconductor device, theelectrical coupling between the power MISFET and the Schottky barrierdiode is performed using a bonding wire so that an increase in aparasitic inductance and deterioration in circuit efficiency of theDC/DC converter occur. Described specifically, owing to the parasiticinductance of a wire and the like present between the power MISFET andthe Schottky barrier diode, electric current temporarily flows throughthe body diode after the power MISFET is turned off, and then commutatesto the Schottky barrier diode with a delay. If this parasitic inductanceis large, it not only retards the commutation speed but also becomes acause of noise and ripples.

In order to reduce this parasitic inductance, there has been atechnology of incorporating a Schottky barrier diode in a semiconductorchip having a power MISFET. According to this technique, the number ofcoupling wires between the power MISFET and the Schottky barrier diodecan be reduced, which leads to a reduction in the parasitic inductance.As a result, the time of a current flowing through the body diode of thepower MISFET can be controlled, and a circuit loss during a dead timecan be considerably reduced in a DC/DC converter controlled by PWM(Pulse Width Modulation). For these reasons, a power MISFET and aSchottky barrier diode are incorporated together in one semiconductorchip.

FIG. 3 is a plan view illustrating an upper surface of a semiconductorchip in which a power MISFET and a Schottky barrier diode areincorporated. In FIG. 3, the semiconductor chip CHP has a rectangularshape and it has, at one corner thereof, a gate pad GP. Elementformation regions are formed in a major part of the semiconductor chipCHP. These element formation regions have a plurality of power MISFETsand between these power MISFETs, Schottky barrier diodes SBDs areplaced. In short, the semiconductor chip has a structure in which linearSchottky barrier diodes SBDs are formed between the power MISFETs.

A drop in the forward voltage (VF) of the Schottky barrier diode SBD isdetermined by the area of the Schottky barrier diode SBD so that thearea of the Schottky barrier diode SBD is determined in order to obtaina predetermined drop in forward voltage (VF). For example, a drop inforward voltage (VF) can be reduced by widening the total area of theplural Schottky barrier diodes SBDs. FIG. 3 illustrates a plurality oflinear Schottky barrier diodes inserted in order to increase the totalarea of the Schottky barrier diodes. The total area of the pluralSchottky barrier diodes SBDs can also be increased by widening the linewidth of the linear Schottky barrier diodes SBDs.

FIG. 4 is a plan view illustrating another method of adjusting the areaof a Schottky barrier diode SBD. FIG. 4 illustrates a Schottky barrierdiode SBD sandwiched between power MISFETs. A drop in forward voltage(VF) of the Schottky barrier diode SBD is adjusted by increasing thearea of this Schottky barrier diode. In FIG. 3, the total area of theplural Schottky barrier diodes SBDs is increased by inserting aplurality of Schottky barrier diodes having a linear form. In FIG. 4, onthe other hand, only one thick Schottky barrier diode SBD having alinear form is inserted and by widening the line width of thethus-inserted Schottky barrier diode, an area of the Schottky barrierdiode SBD is increased.

Thus, for adjusting the area of the Schottky barrier diode SBD, theabove-described two means can be considered, that is, a means of forminga plurality of thin and linear Schottky barrier diodes SBDs to increasethe total area of the Schottky barrier diodes SBDs and a means offorming one thick and linear Schottky barrier diode SBD and increasingthe line width thereof to increase the total area of the Schottkybarrier diode SBD. Either one can be employed for adjusting the totalarea of the Schottky barrier diode SBD. As a result, a drop in forwardvoltage (VF) of the Schottky barrier diode SBD can be adjusted.

Formation of a plurality of thin and linear Schottky barrier diodes SBDsas illustrated in FIG. 3 has however the following advantage overformation of one thick and linear Schottky barrier diode SBD asillustrated in FIG. 4. This advantage will hereinafter be described.Although not illustrated in FIGS. 3 and 4, a source electrode is formedover the power MISFET and the Schottky barrier diode SBD, while a drainelectrode is formed on the back side of the semiconductor chip CHP. Inthe power MISEFT, current therefore flows in a direction vertical to thepaper surface (thickness direction of the semiconductor chip CHP). Atthis time, the formation region of the Schottky barrier diode SBD is notused as a pathway for the current flowing through the power MISFET. Morespecifically, in the structure illustrated in FIG. 4, since the Schottkybarrier diode SBD has a very large line width, this region is not usedas a pathway for the current flowing through the power MISFET. In thestructure illustrated in FIG. 3, on the other hand, since the Schottkybarrier diode SBD has a small line width, a pathway for current flowingthrough the power MISFET is formed so that it enters the formationregion of the Schottky barrier diode SBD from both sides. The formationregions of Schottky barrier diodes SBDs having a small line width canalso be used as a current pathway. This means an increase in the numberof pathways for the current flowing through the power MISFET. As aresult, the on-resistance of the power MISFET can be reduced.

Described specifically, even in the structure illustrated in FIG. 4, acurrent pathway for the current flowing through the power MISFET entersthe formation region of the Schottky barrier diode SBD but the currentpathway does not reach the center region of the Schottky barrier diodeSBD because the Schottky barrier diode SBD has a very large line width.In the structure illustrated in FIG. 3, on the other hand, since theSchottky barrier diode SBD has a very small line width, current pathwaysenter the Schottky barrier diode SBD from boundary regions on both sidesof the power MISFETs having the Schottky barrier diode SBD therebetweenand the current pathways from the boundary regions on both sides thereofmerge together. In short, all the formation regions of the Schottkybarrier diode SBD are used as a current pathway for the current flowingthrough the power MISFET. This phenomenon occurs in the plural Schottkybarrier diodes SBDs in the linear form so that the whole region of theplural linear Schottky barrier diodes SBDs can be used as a currentpathway for the current flowing through the power MISFET.

By forming a plurality of thin and linear Schottky barrier diodes SBDs,thereby increasing the total area of the Schottky barrier diodes SBDs asillustrated in FIG. 3, the on-resistance of the power MISFET can be madelower than by widening the line width of the Schottky barrier diode SBD,thereby increasing the total area thereof as illustrated in FIG. 4.

In Embodiment 1, two means are described as a means for adjusting thearea of the Schottky barrier diode, that is, a means of forming aplurality of linear Schottky barrier diodes SBDs to increase the totalarea of the Schottky barrier diodes SBDs and a means of forming a thickand linear Schottky barrier diode SBD and widening this line width toincrease the total area of the Schottky barrier diode SBD. It is alsopossible to use these two means in combination in order to adjust thearea of the Schottky barrier diodes SBDs. Described specifically, aplurality of linear Schottky barrier diodes SBDs is formed and the widthof each of the lines of the Schottky barrier diodes SBDs is increased,whereby the area of the Schottky barrier diodes SBDs can be adjusted.

In Patent Document 2, for example, the distance between trenches havinga Schottky barrier diode SBR sandwiched therebetween is made narrowerthan the distance between trenches of cells in which a power MISFET hasbeen formed. Narrowing of the distance between trenches having theSchottky barrier diode SBR sandwiched therebetween is effective forreducing a field intensity on the surface of an epitaxial region inwhich a Schottky junction is formed (RESURF effect). In Patent Document2, this RESURF effect is utilized to improve the avalanche breakdownvoltage of the Schottky barrier diode. In this case, the area of theSchottky barrier diode formation region can be adjusted only by forminga plurality of thin and linear Schottky barrier diodes SBDs, because theRESURF effect cannot be achieved when the area of Schottky barrier diodeSBD is adjusted by increasing the line width. This leads to a loss offreedom to adjust the area of the Schottky barrier diode.

In Embodiment 1, on the other hand, the Schottky barrier diode can havean improved avalanche breakdown voltage without utilizing a RESURFeffect as described later so that for the semiconductor device of thisEmbodiment 1, a means of increasing the line width, thereby adjustingthe area of the Schottky barrier diode SBD can be employed. In thisEmbodiment 1, it is also possible to adjust the area of the Schottkybarrier diode SBD by forming a plurality of Schottky barrier diodes SBDsin line form and increasing the line width of the Schottky barrierdiodes SBDs formed in line form. In short, this Embodiment 1 can providean advantage of enhancing the freedom to adjust the area of the Schottkybarrier diode.

FIG. 5 is an enlarged plan view of the region RC of FIG. 3. Asillustrated in FIG. 5, the Schottky barrier diode SBD formation regionis sandwiched between the power MISFET formation regions. The Schottkybarrier diode SBD formation region has therein an epitaxial layer(second semiconductor) epi2. This epitaxial layer epi2 is an n type(first conductivity type) semiconductor layer doped with n typeimpurities such as phosphorus or arsenic and the epitaxial layer epi2 issandwiched by p rings PRs. The p rings PRs are made of, for example, a ptype (second conductivity type) semiconductor layer doped with p typeimpurities such as boron.

The p rings PRs are sandwiched between trenches Ts and a conductive filmsuch as a polysilicon film is filled in the trenches Ts to serve as agate electrode G of the power MISFET. The Schottky barrier diodeformation region SBD is a region sandwiched between these trenches T andthe Schottky barrier diode SBD formation region includes the epitaxiallayer epi2 and the p rings PRs having the epitaxial layer epi2sandwiched therebetween. Regions outside the trenches Ts but includingthe trenches Ts are power MISFET formation regions.

The power MISFET formation regions have therein source regions SRsformed outside the trenches Ts and adjacent to the trenches Ts. Thesesource regions SRs are made of an n type semiconductor region andfunction as source regions of the power MISFET. The source regions SRshave, outside and adjacent thereto, body contact regions BCs. The bodycontact regions BCs are made of a p type semiconductor region. The bodycontact regions BCs have, outside thereof, source regions SRs and thesesource regions ST have, outside thereof, trenches T. Similarly, thetrenches Ts have, outside thereof, source regions SRs and body contactregions BCs. In short, the power MISFET formation region has therein acell (one power MISFET) including the trench T (gate electrode G), thesource region SR, and the body contact region BC and with this structureas a unit, the power MISFET formation region has a plurality of cellsarranged therein.

FIG. 6 is a cross-sectional view taken along a line X-X of FIG. 5.Referring to FIG. 6, the configuration of the power MISFET formed in thepower MISFET formation region and the Schottky barrier diode SBD formedin the Schottky barrier diode formation region will next be described infurther detail.

First, the configuration of the power MISFET formed in the power MISFETformation region is described referring to FIG. 6. As illustrated inFIG. 6, the power MISFET formation region has therein a semiconductorsubstrate 1S doped with, for example, n type impurities and thissemiconductor substrate 1S has thereover an epitaxial layer epi1. Thisepitaxial layer epi1 is an n type semiconductor layer doped with n typeimpurities. The epitaxial layer epi1 has thereover a channel region CH.The channel region CH is a p type semiconductor region doped with p typeimpurities.

Further, the power MISFET formation region has therein a trench Tpenetrating through the channel region CH and reaching the epitaxiallayer epi1. The trench T has, over the inner wall of the trench T, agate insulating film GOX made of, for example, a silicon oxide film anda gate electrode G is filled in the trench T via this gate insulatingfilm GOX. The gate electrode G is made of, for example, a polysiliconfilm.

A region above the channel region CH and adjacent to the trench T hastherein a source region SR. Upper portions of the source region SR andthe trench T are covered with an interlayer insulating film IL. Althoughthe gate electrode G protrudes from the trench T, the interlayerinsulating film IL covers even this gate electrode G therewith.

The interlayer insulating film 1L has therein a contact hole C1 and thiscontact hole C1 penetrates through the interlayer insulating film IL andthe source region SR. Due to the presence of the contact hole C1, thesource region SR is located in a region between the contact hole C1 andthe trench T and is adjacent to both the contact hole C1 and the trenchT.

The contact hole C1 has, therebelow, a body contact region BC. Thismeans that the body contact region BC comes in contact with the bottomportion of the contact hole C1 and below the bottom portion. The bodycontact region BC is made of a p type semiconductor region doped with ptype impurities and it is more heavily doped with p-type impurities thanthe channel region CH also made of the p type semiconductor region. Thebody contact region BC has a function of ensuring an ohmic contact witha source electrode formed by filling a conductive film in the contacthole C1 and a function of suppressing the on-operation of a parasiticbipolar transistor at the power MISFET. Described specifically, in atrench gate type power MISFET, an npn parasitic bipolar transistor isformed from the source region SR (which will be an emitter) which is ann type semiconductor region, the channel region CH (which will be abase) which is a p type semiconductor region, and the epitaxial layerepi1 (which will be a collector) which is an n type semiconductorregion. By the on-operation of this npn parasitic bipolar transistor, acurrent too large to be controlled by the gate electrode G of the powerMISFET flows under some operation environments. As a result, the powerMISFET generates excessive heat, leading to destruction. It is thereforenecessary to prevent the on-operation of the npn parasitic bipolartransistor. A base resistance should be minimized in order to suppressthe on-operation of the npn parasitic bipolar transistor. In view ofthis, the base resistance is reduced by forming the body contact regionBC having a higher doping concentration than that of the channel regionCH.

The body contact region BC has therebelow a first semiconductor regionP1. This first semiconductor region P1 is made of a p type semiconductorregion and it is doped with p type impurities at a doping concentrationso as to have a lower doping concentration than that of the body contactregion BC but a higher doping concentration than that of the channelregion CH. The first semiconductor region P1 extends even in a regiondeeper than the boundary between the channel region CH and the epitaxiallayer epi1.

The first semiconductor region P1 thus formed can relax fieldconcentration at a pn junction formed at the boundary between thechannel region CH and the epitaxial layer epi1 and increase an avalanchebreakdown voltage of the power MISFET. In other words, it is possible toimprove the breakdown voltage of the power MISFET. The “breakdownvoltage” (BVdss) of the power MISFET as used herein is determined by avoltage at which avalanche breakdown occurs when a voltage is applied tothe drain region while the gate electrode G and the source region SR aregrounded. Thus, the first semiconductor region P1 formed below the bodycontact region BC has a function of improving the breakdown voltage ofthe power MISFET.

The term “avalanche breakdown voltage” as used herein means a voltage atwhich an avalanche breakdown phenomenon occurs when a reverse voltage (avoltage applied in a direction for increasing a potential barrier formedat a junction) is applied to a pn junction or a Schottky junction. Theavalanche breakdown phenomenon occurs via the following mechanism.Described specifically, in a depletion layer formed in a junction,electrons and holes accelerated by a high electric field are caused tocollide with crystal lattices. By the collision, covalent bonds whichcouple the crystal lattices therewith are broken and generate new pairsof an electron and a hole (impact ionization). These new electron-holepairs gain energy from the high electric field, collide with crystallattices, and generate new electron-hole pairs again. Thismultiplication phenomenon leads to flow of a large current through thedepletion layer. This phenomenon is called “avalanche breakdownphenomenon”.

The interlayer insulating film IL containing the inside of the contacthole C1 has thereover a titanium tungsten film 5 a and the titaniumtungsten film 5 a has thereover an aluminum film 5 b. The titaniumtungsten film 5 a and the aluminum film 5 b configure a first metal film6. The first metal film 6 is filled in the contact hole C1 andelectrically coupled to the source region SR and the body contact regionBC. This suggests that the first metal film 6 therefore functions as asource electrode of the power MISFET in the power MISFET formationregion.

The semiconductor substrate 1S has, over the back side thereof, a secondmetal film 7. This second metal film 7 is made of, for example, a goldfilm and it functions, in the power MISFET formation region, as a drainelectrode of the power MISFET.

In such a manner, the power MISFET formation region has therein thepower MISFET. In the power MISFET having the above-described structure,the structure requires formation of a body diode BD. As described above,the first metal film 6 is filled in the contact hole C1 and the firstmetal film 6 filled in the contact hole C1 is electrically coupled tothe body contact region BC. The body contact region BC and a firstsemiconductor region P1 formed below the body contact region BC are bothp type semiconductor layers so that the body contact region BC iselectrically coupled to the first semiconductor region P1. The firstsemiconductor region P1 is therefore coupled to the first metal film 6which will be a source electrode.

The epitaxial layer epi1 which is an n type semiconductor region iscontiguous to the bottom layer of the first semiconductor region P1 sothat a pn junction is formed at a boundary between the firstsemiconductor region P1 and the epitaxial layer epi1. The epitaxiallayer epi1 lies over the semiconductor substrate 1S which is an n typesimilarly. This semiconductor substrate 1S has, on the back sidethereof, a second metal film 7. The epitaxial layer epi1 is thereforeelectrically coupled to the second metal film 7 which will be a drainelectrode.

This means that the first semiconductor region P1 and the epitaxiallayer epi1 configure a pn junction, the first semiconductor region P1 iscoupled to the source electrode and the epitaxial layer epi1 is coupledto the drain electrode. This suggests that a body diode BD which is a pnjunction diode is formed between the source electrode and the drainelectrode. In this body diode BD, the source electrode serves as ananode electrode and the drain electrode serves as a cathode electrode sothat a current flows from the source electrode to the drain electrode.

The power MISFET has the configuration as described above. Its operationwill hereinafter be described briefly. For example, a voltage equal toor greater than the threshold voltage of the gate electrode G is appliedwhile giving a potential difference between the source electrode and thedrain electrode. Then, an inversion layer is formed in the channelregion CH contiguous to the side surface of the trench T filled with thegate electrode G. In other words, an inversion layer which is an n typesemiconductor region is formed in a region of the channel region CH,which is a p type semiconductor region, contiguous to the trench T.Then, the source region SR which is an n type semiconductor region andthe epitaxial layer epi1 which is an n type semiconductor layer areelectrically coupled to each other via the inversion layer. A potentialdifference is therefore applied to the source electrode and the drainelectrode, whereby a current flows between the source electrode and thedrain electrode.

For example, when the power MISFET is the synchronous-rectificationpower MISFET Q2 illustrated in FIG. 1, the direction of the currentflowing during the term of B is the direction of the arrow of FIG. 1 sothat a current flows from the source electrode of the power MISFET tothe drain electrode thereof. In other words, when a voltage equal to orgreater than the threshold voltage is applied to the gate electrode Gwhile setting the potential of the source electrode greater than thepotential of the drain electrode, the current flows from the sourceelectrode, passes through the source region and the inversion layer,passes further through the epitaxial layer epi1 which is a drift layerand the semiconductor substrate 1S, and reaches the drain electrode. Insuch a manner, the power MISFET is turned on. At this time, theepitaxial layer epi1 becomes a drift layer, suggesting that theepitaxial layer epi1 preferably has a high doping concentration from thestandpoint of reducing the on-resistance of the power MISFET.

When a voltage to be applied to the gate electrode G is set not greaterthan the threshold voltage while turning on the power MISFET, theinversion layer disappears. The power MISFET is therefore turned off. Inthe case as illustrated in FIG. 1, however, the inductance L tries tokeep the current flowing during the term of B. Since the body diode BDcan pass a current from the source electrode to the drain electrode, thebody diode BD formed for the structural reason of the power MISFETenables a current flow from the source electrode to the drain electrodeeven if the power MISFET is turned off. In the DC/DC converterillustrated in FIG. 1 having such a mechanism, the body diode BDcontributes to the flow of current even during a dead time.

A voltage drop when forward current flows through the body diode BD isnot a negligible level. A circuit loss caused by a current flowingthrough the body diode BD during a dead time cannot therefore beneglected.

A Schottky barrier diode SBD is therefore formed over the semiconductorsubstrate 1S over which the power MISFET is formed. The Schottky barrierdiode SBD can reduce a circuit loss during a dead time, because a dropof a forward voltage (VF) is lower than that of a pn junction diode(body diode BD).

Referring to FIG. 6, the configuration of the Schottky barrier diode SBDformed in the Schottky barrier diode SBD formation region will next bedescribed. As illustrated in FIG. 6, the Schottky barrier diode SBDformation region has therein a semiconductor substrate 1S doped with,for example, n type impurities and this semiconductor substrate 1S has,thereover, an epitaxial layer epi1. The epitaxial layer epi1 hasthereover an epitaxial layer epi2. The epitaxial layer epi1 and theepitaxial layer epi2 are each an n type semiconductor layer doped with ntype impurities and the doping concentration of the epitaxial layer epi2is lower than that of the epitaxial layer epi1.

The epitaxial layer epi2 has, thereover, a contact hole C2 which isformed by partially opening the interlayer insulating film IL andepitaxial layer epi2. This means that the contact hole C2 has therebelowthe epitaxial layer epi2. The contact hole C2 has therein a first metalfilm 6 made of a titanium tungsten film (barrier conductor film) 5 a andan aluminum film 5 b. Such a configuration brings the epitaxial layerepi2 into contact with the first metal film 6 at the bottom portion ofthe contact hole C2. More specifically, the epitaxial layer epi2 comesinto direct contact with the titanium tungsten film 5 a configuring thefirst metal film 6, meaning that a semiconductor layer comes intocontact with a metal film, whereby a Schottky junction is formed.

Not only the interlayer insulating film IL but also a portion of theepitaxial layer 2 from the surface to a predetermined depth has anopening as the contact hole C2, because the contact hole C2 is formed ina similar step to that employed for the formation of the contact hole C1to be formed in the power MISFET formation region. This means that thecontact hole C1 to be formed in the power MISFET formation region shouldpenetrate through the source region SR and the semiconductor layerhaving therein the source region SR should be opened to a predetermineddepth. Also in the contact hole C2 formed in a similar step to that ofthe contact hole C1, the epitaxial layer epi2 is therefore opened to apredetermined depth.

Since the epitaxial layer epi2 is opened to a predetermined depth by thecontact hole C2, phosphorus segregated to the surface of the epitaxiallayer epi2 can be removed by a heat treatment step. This means that whenthe epitaxial layer epi2 is not opened to a predetermined depth by thecontact hole C2, a Schottky junction is formed in a region of theepitaxial layer epi2 having phosphorus segregated thereto. Due tophosphorus thus segregated, the doping concentration of thesemiconductor layer forming a Schottky junction becomes high. Thisinconveniently causes a reduction in an avalanche breakdown voltage ofthe Schottky barrier diode SBD. It is therefore possible to suppress areduction in the avalanche breakdown voltage of the Schottky barrierdiode SBD by removing a phosphorus segregated region of the epitaxiallayer epi2 by the contact hole C2.

The first metal film 6 filled in the contact hole C2 contains thetitanium tungsten film 5 a configuring one (metal film side) of theSchottky junction so that it functions as an anode electrode of theSchottky barrier diode SBD. In other words, the first metal film 6 isformed over the power MISFET formation region and the Schottky barrierdiode SBD formation region so that it functions as a source electrode inthe power MISFET formation region and as an anode electrode in theSchottky barrier diode SBD formation region.

The semiconductor substrate 1S has, over the back side thereof, a secondmetal film 7 made of, for example, a gold film. This second metal film 7is electrically coupled to the epitaxial layer epi2 via the n typesemiconductor substrate 1S and the epitaxial layer epi1 which is an ntype semiconductor layer. The second metal film 7 therefore functions asa cathode electrode of the Schottky barrier diode SBD. This means thatthe second metal film 7 is formed over the power MISFET formation regionand the Schottky barrier diode SBD formation region and it functions asa drain electrode in the power MISFET formation region and as a cathodeelectrode in the Schottky barrier diode SBD formation region.

The Schottky barrier diode SBD according to Embodiment 1 has theabove-described configuration and it is coupled in parallel to the powerMISFET. A drop of forward voltage (VF) of the Schottky barrier diode islower than a drop of forward voltage (VF) of the body diode BD formedparasitically in the power MISFET so that parallel coupling between theSchottky barrier diode SBD and the power MISFET enables to reduce acircuit loss during the dead time of a DC/DC converter.

The Schottky barrier diode SBD formation region has p rings PRs betweenthe epitaxial layer epi2 and trenches on both sides. It is formedbecause contact between the epitaxial layer epi2 and the trenches T onboth sides increases a leakage current flowing through the Schottkybarrier diode SBD. In other words, the amount of a leakage currentcaused by the application of a reverse voltage to the Schottky barrierdiode SBD increases when the epitaxial layer epi2 is brought intocontact with the trench T. In Embodiment 1, the p rings PRs made of a ptype semiconductor region is therefore formed between the epitaxiallayer epi2 and the trenches T on both sides. This enables to reduce aleakage current which occurs when a reverse voltage is applied to theSchottky barrier diode SBD.

The semiconductor device according to Embodiment 1 has theabove-described configuration and characteristics of it will next bedescribed. One of the characteristics of Embodiment 1 is that theepitaxial layer formed over the semiconductor substrate 1S is composedof two layers, that is, a heavily-doped epitaxial layer epi1 and alightly-doped epitaxial layer epi2 and the boundary between theepitaxial layer epi1 and the epitaxial layer epi2 is located at aposition as deep as the bottom portion of the trench T or shallower thanthe bottom portion of the trench T.

Supposing that the epitaxial layer formed over the semiconductorsubstrate 1S is composed of only the epitaxial layer epi1 having a highdoping concentration. In this case, in the power MISFET formationregion, the doping concentration of the epitaxial layer epi1 formed in aregion deeper than the trench T becomes high. When the power MISFET isturned on, the epitaxial layer epi1 located lower than the trench Tbecomes a drift layer. The doping concentration of this drift layerbecomes high so that the on-resistance of the power MISFET can bereduced.

The Schottky junction of the Schottky barrier diode SBD is, on the otherhand, formed by the epitaxial layer epi1 having a high dopingconcentration and the titanium tungsten film 5 a. When the epitaxiallayer epi1 forming a Schottky junction has a high doping concentration,the field intensity in the vicinity of the Schottky junction increases,leading to a reduction in the breakdown voltage of the Schottky barrierdiode SBD. The reduction in the breakdown voltage of the Schottkybarrier diode SBD means a reduction in the avalanche breakdown voltageof the Schottky barrier diode SBD.

When the avalanche breakdown voltage of the Schottky barrier diode SBDreduces, the avalanche breakdown voltage of the Schottky barrier diodeSBD becomes lower than the avalanche breakdown voltage (breakdownvoltage) of the power MISFET. Described specifically, when both theSchottky barrier diode SBD and the power MISFET are formed over thesemiconductor substrate 1S, the Schottky barrier diode SBD causesavalanche breakdown at a voltage lower than the power MISFET. In otherwords, the avalanche breakdown of the Schottky barrier diode SBD occursprior to the avalanche breakdown of the power MISFET. This means thatthe breakdown voltage of a semiconductor device having the power MISFETand the Schottky barrier diode over the same semiconductor substrate 1Sbecomes lower than the breakdown voltage of the semiconductor devicehaving only the power MISFET over the semiconductor substrate 1S and thesemiconductor device has deteriorated reliability by having the powerMISFET and Schottky barrier diode over the same semiconductor substrate1S. Formation of the power MISFET and the Schottky barrier diode SBDover the epitaxial layer epi1 having a high doping concentration leadsto reduction in the on-resistance of the power MISFET, but it also leadsto reduction in the avalanche breakdown voltage of the Schottky barrierdiode inconveniently.

Supposing that the epitaxial layer formed over the semiconductorsubstrate 1S is composed only of the epitaxial layer epi2 having a lowdoping concentration. In this case, the Schottky junction of theSchottky barrier diode SBD is formed by the epitaxial layer epi2 havinga low doping concentration and the titanium tungsten film 5 a. When thedoping concentration of the epitaxial layer epi2 configuring theSchottky junction is low, a field intensity in the vicinity of theSchottky junction can be relaxed, leading to an increase in theavalanche breakdown voltage of the Schottky barrier diode SBD. Theavalanche breakdown voltage of the Schottky barrier diode SBD cantherefore be made higher than the avalanche breakdown voltage of thepower MISFET. This means that even if both the power MISFET and theSchottky barrier diode SBD are formed over the same semiconductorsubstrate 1S, the breakdown voltage is on an equal level to thatattained by the formation of only the power MISFET over thesemiconductor substrate 1S. As a result, deterioration in reliability ofthe semiconductor device can be suppressed.

In the power MISFET formation region, however, the doping concentrationof the epitaxial layer epi2 formed in a region deeper than the trench Tbecomes low. When the power MISFET is turned on, the epitaxial layerepi2 formed lower than the trench T becomes a drift layer. The impurityconcentration of this drift layer becomes low so that the on-resistanceof the power MISFET increases inconveniently.

Although an increase in the doping concentration of the epitaxial layercauses a reduction in the on-resistance of the power MISFET, it alsocauses a reduction in the avalanche breakdown voltage of the Schottkybarrier diode SBD, resulting in that the avalanche breakdown voltage ofthe Schottky barrier diode SBD becomes lower than the avalanchebreakdown voltage of the power MISFET. A decrease in the dopingconcentration of the epitaxial layer, on the other hand, can raise theavalanche breakdown voltage of the Schottky barrier diode SBD, resultingin that the avalanche breakdown voltage of the Schottky barrier diodeSBD can be made higher than the avalanche breakdown voltage of the powerMISFET. It however increases the on-resistance of the power MISFET. Thismeans that with regards to the doping concentration of the epitaxiallayer, a decrease in the on-resistance of the power MISFET and anincrease in the avalanche breakdown voltage of the Schottky barrierdiode are in a trade-off relationship.

Embodiment 1 takes both an advantage of an epitaxial layer whose dopingconcentration is made high and an advantage of another epitaxial layerwhose doping concentration is made low. Described specifically, twoepitaxial layers, that is, the epitaxial layer epi1 having a high dopingconcentration and the epitaxial layer epi2 having a low dopingconcentration are formed over the semiconductor substrate 1S and aboundary between the epitaxial layer epi1 and the epitaxial layer epi2is formed in a region equal to the bottom portion of the trench T orshallower than the bottom portion of the trench T.

According to such a configuration, the epitaxial layer epi2 having a lowdoping concentration and the titanium tungsten film 5 a form a Schottkyjunction in the Schottky barrier diode SBD formation region. Describedspecifically, since the epitaxial layer epi2 is formed in a region equalto or above the bottom portion of the trench, the epitaxial layer epi2does not become a drift layer of the power MISFET and has no influenceon the on-resistance of the power MISFET. This means that the dopingconcentration of the epitaxial layer epi2 can be determined only fromthe standpoint of raising the avalanche breakdown voltage of theSchottky barrier diode SBD. Embodiment 1, therefore, enables to increasethe avalanche breakdown voltage of the Schottky barrier diode SBD,resulting in that the avalanche breakdown voltage of the Schottkybarrier diode SBD can be made higher than the avalanche breakdownvoltage of the power MISFET.

Moreover, in Embodiment 1, the epitaxial layer epitaxial layer epi2 has,therebelow, the epitaxial layer epi1 having a high doping concentration.This epitaxial layer epi1 is formed in a region equal to or deeper thanthe depth of the trench T and it therefore functions as a drift layer ofthe power MISFET in the power MISFET formation region. At this time, theepitaxial layer epi1 does not function as a semiconductor layer forforming the Schottky junction of the Schottky barrier diode SBD. It istherefore possible to determine the epitaxial layer epi1 from thestandpoint of reducing the on-resistance of the power MISFET withoutconsidering an increase in the avalanche breakdown voltage of theSchottky barrier diode SBD. The impurity concentration of the epitaxiallayer epi1 can be made high enough to reduce the on-resistance of thepower MISFET sufficiently.

The epitaxial layer epi1 having a high doping concentration hasthereover the epitaxial layer epi2 having a low doping concentration,but as illustrated in FIG. 6, in the power MISFET formation region, itseems that no epitaxial layer epi2 is formed. The reason is that, in thepower MISFET formation region, a channel region CH which is a p typesemiconductor region is formed by introducing, into the epitaxial layerepi2 which is an n type semiconductor layer, p type impurities having aconductivity type opposite thereto. It is therefore presumed that in thepower MISFET formation region, the epitaxial layer epi2 having a lowdoping concentration completely becomes the channel region CH which is ap type semiconductor region. Thus, in the power MISFET formation region,by changing the epitaxial layer epi2 having a low doping concentrationto the channel region CH, the influence of the epitaxial layer epi2 onthe on-resistance of the power MISFET can be omitted. In order tocompletely change the epitaxial layer epi2 to the channel region CH, itis desirable to make the boundary between the epitaxial layer epi1 andthe epitaxial layer epi2 shallower than the depth of the channel regionCH from the standpoint of reducing the on-resistance of the powerMISFET. In Embodiment 1, it is necessary to form the boundary betweenthe epitaxial layer epi1 and the epitaxial layer epi2 in a region equalin depth to the bottom portion of the trench T or shallower than thebottom portion of the trench T. Even in this case, however, when theboundary between the epitaxial layer epi1 and the epitaxial layer epi2is present in a region deeper than the channel region CH, the epitaxiallayer epi2 configures a portion of a drift layer and contributes to theon-resistance.

In Embodiment 1, two epitaxial layers, that is, the epitaxial layer epi1having a high doping concentration and the epitaxial layer epi2 having alow doping concentration are formed over the semiconductor substrate 1Sand the boundary between the epitaxial layer epi1 and the epitaxiallayer epi2 is formed in a region equal in depth to the bottom portion ofthe trench T or shallower than the bottom portion of the trench T.Embodiment 1 therefore has a marked effect for realizing both reductionin the on-resistance of the power MISFET and improvement in theavalanche breakdown voltage of the Schottky barrier diode SBD which arein a trade-off relationship.

In this embodiment, the epitaxial layer epi1 having a high dopingconcentration has thereover the epitaxial layer epi2 having a low dopingconcentration. The definition of the boundary between the epitaxiallayer epi1 and the epitaxial layer epi2 will next be described.

For example, immediately after the formation of the epitaxial layer epi1and the epitaxial layer epi2, the boundary between the epitaxial layerepi1 and the epitaxial layer epi2 is relatively definite because thedoping concentration varies in a relatively stepwise manner between theepitaxial layer epi1 and the epitaxial layer epi2. Manufacturing stepsof the semiconductor device include various heat treatment stepsthereafter so that impurities diffuse in the epitaxial layer epi2 havinga low doping concentration from the epitaxial layer epi1 having a highdoping concentration. As a result, there occurs a gradual change in thedoping concentration at the boundary between the epitaxial layer epi1and the epitaxial layer epi2 and the boundary between the episemiconductor substrate 1 and the epitaxial layer epi2 becomesindefinite. The boundary between the epitaxial layer epi1 and theepitaxial layer epi2 will therefore be defined in order to clarify theboundary between the epitaxial layer epi1 and epitaxial layer epi2 evenafter completion of the semiconductor device. This definition willhereinafter be described.

FIG. 7 is a graph showing a change in the doping concentration along theline D1-D1 of FIG. 6. The change in the doping concentration shown inthis graph is a change from the surface of the epitaxial layer epi2 tothe semiconductor substrate 1S in the structure (complete structure) ofFIG. 6 obtained by forming the epitaxial layer epi1 over thesemiconductor substrate 1S and then forming the epitaxial layer epi2over the epitaxial layer epi1.

In FIG. 7, the doping concentration of n type impurities in a regionwhere the depth from the surface of the epitaxial layer epi2 is shallowis designated as a first concentration. The first doping concentrationis kept almost fixed until a predetermined depth. As the depth becomesgreater, the doping concentration gradually increases from the firstconcentration to a second concentration. As the depth becomes greater,the doping concentration shows a further increase from the secondconcentration and becomes a substrate concentration.

The substrate concentration at this time is, for example, from 2×10¹⁹(1/cm³) to 7×10¹⁹ (1/cm³) and it is the concentration of thesemiconductor substrate 1S. This substrate concentration is determinedby the maximum possible concentration of the doping concentration andaccording to the present crystal technology, the concentration is about4×10¹⁹ (1/cm³) when the impurity is arsenic, while it is about 7×10¹⁹(1/cm³) when the impurity is phosphorus.

The boundary between the semiconductor substrate 1S and the epitaxiallayer epi1 is represented by B1. The substrate concentration decreasesby half at the position B1. This means that the boundary between thesemiconductor substrate 1S and the epitaxial layer epi1 is defined as aposition where the doping concentration decreases to half (½) of thesubstrate concentration.

The second concentration is from 2×10¹⁶ (1/cm³) to 4×10¹⁶ (1/cm³) and itis the concentration in the epitaxial layer epi1. This epitaxial layerepi1 has a width and concentration necessary for keeping the avalanchebreakdown voltage of the power MISFET at 30V or greater. The secondconcentration corresponds to a doping concentration at which theconcentration gradient (obtained by differentiating a dopingconcentration with respect to depth) becomes the minimum between theposition corresponding to the depth of the trench T to the boundary withthe semiconductor substrate 1S. The boundary between the epitaxial layerepi1 and the epitaxial layer epi2 is defined as a position at which thedoping concentration decreases by half (½) of the second concentration.The position of the boundary is indicated as B2 in FIG. 7. The epitaxiallayer epi1 having a high doping concentration can be defined as a regionformed in a region deeper than the position B2 but shallower than theposition B1. Although the width of this epitaxial layer epi1 depends onthe impurities rising up from the semiconductor substrate 1S, it can beset at from about 2.0 to 3.0 μm for adjusting the avalanche breakdownvoltage of the power MISFET to 30V or greater. Care should be taken soas not to excessively increase the width of the epitaxial layer epi1,because it may raise a series resistance of the Schottky barrier diodeor the on-resistance of the power MISFET.

Next, the first concentration is a doping concentration in the vicinityof the surface of the epitaxial layer epi2. The first concentration is aconcentration for making the avalanche breakdown voltage of the Schottkybarrier diode SBD higher than the avalanche breakdown voltage of thepower MISFET. More specifically, the first concentration is preferablyadjusted to 8.0×10¹⁵ (1/cm³) or less. The boundary between the epitaxiallayer epi1 and the epitaxial layer epi2 is defined as the position ofB2. In Embodiment 1, the position of B2 is set equal to or shallowerthan the depth of the trench T.

In FIG. 7, the doping concentration from the vicinity of the surface ofthe epitaxial layer epi2 to a predetermined depth is almost fixed at thefirst concentration. This is because the rising-up of the impuritiesfrom the epitaxial layer epi1 does not reach a region of a fixed dopingconcentration. When the doping concentration of the epitaxial layer epi2in the vicinity of the surface thereof is not higher than the firstconcentration (8.0×10¹⁵ (1/cm³)) even if the impurities from theepitaxial layer epi1 rise up and reach the vicinity of the surface ofthe epitaxial layer epi2, the avalanche breakdown voltage of theSchottky barrier diode SBD can be made higher than the avalanchebreakdown voltage of the power MISFET. In other words, when the dopingconcentration of the epitaxial layer epi2 in the vicinity of the surfacethereof is the first concentration or less, the avalanche breakdownvoltage of the Schottky barrier diode SBD can be made higher than theavalanche breakdown voltage of the power MISFET irrespective of thepresence of a region where the doping concentration is almost fixed.

In Embodiment 1, the doping concentration of the epitaxial layer epi2 inthe vicinity of the surface thereof is set at 8.0×10¹⁵ (1/cm³) or less.The reason why it is set at this value will next be described referringto FIG. 8.

FIG. 8 is a graph showing a relationship between a doping concentrationof the surface of the epitaxial layer epi2 (second semiconductor layer)and an avalanche breakdown voltage. In FIG. 8, the doping concentrationof the epitaxial layer epi2 (second semiconductor layer) is plotted onthe abscissa and the avalanche breakdown voltage is plotted on theordinate. The solid circle of FIG. 8 represents a Schottky barrier diodeSBD and a blank circle of FIG. 8 represents a power MISFET. The graph ofFIG. 8 is based on a structure obtained by forming an epitaxial layerepi1 and an epitaxial layer epi2 over a semiconductor substrate 1S andplacing the boundary between the epitaxial layer epi1 and the epitaxiallayer epi2 in a region equal to or shallower than the depth of a trenchT, as illustrated in FIG. 6, and it plots an avalanche breakdown voltageof the Schottky barrier diode SBD and an avalanche breakdown voltage ofthe power MISFET at varied doping concentrations of the epitaxial layerepi2.

As is apparent from FIG. 8, the avalanche breakdown voltage of theSchottky barrier diode SBD and the avalanche breakdown voltage of thepower MISFET each increases with a reduction in the doping concentrationof the epitaxial layer epi2. The avalanche breakdown voltage of theSchottky barrier diode SBD and the avalanche breakdown voltage of thepower MISFET substantially coincide with each other at a dopingconcentration of the epitaxial layer epi2 of about 8.0×10¹⁵ (1/cm³).Further, FIG. 8 has revealed that the avalanche breakdown voltage of theSchottky barrier diode SBD becomes higher than the avalanche breakdownvoltage of the power MISFET at a doping concentration of the epitaxiallayer epi2 lower than 8.0×10¹⁵ (1/cm³). As a result, it is possible tomake the avalanche breakdown voltage of the Schottky barrier diode SBDhigher than the avalanche breakdown voltage of the power MISFET byadjusting the doping concentration of the epitaxial layer epi2 in thevicinity of the surface thereof to not higher than 8.0×10¹⁵ (1/cm³).

FIG. 9 is a graph showing a change in doping concentration along a lineD2-D2 of FIG. 6. This change in doping concentration shows a change fromthe surface of the body contact region BC to the semiconductor substrate1S in a structure (complete structure) obtained by forming an epitaxiallayer epi1 over a semiconductor substrate 1S and forming a p typesemiconductor region (first semiconductor region) P1 and a body contactregion BC over the epitaxial layer epi1. FIG. 9 is therefore a graphshowing an impurity profile in a body diode BD.

As illustrated in FIG. 9, the body contact region BC is doped with ptype impurities and a p type semiconductor region P1 formed below thebody contact region BC is also doped with p type impurities. As isapparent from FIG. 9, the concentration of the impurities introducedinto the body contact region BC is much higher than the concentration ofthe impurities introduced into the p type semiconductor region P1 sothat the boundary between the body contact region BC and the p typesemiconductor region P1 is relatively clear. The p type semiconductorregion P1 has therebelow the epitaxial layer epi1 and the epitaxiallayer epi1 is doped with n type impurities different from the p typeimpurities. The boundary between the p type semiconductor region P1 andthe epitaxial layer epi1 is therefore relatively clear.

The epitaxial layer epi1 has therebelow the semiconductor substrate 1S.The boundary between the epitaxial layer epi1 and the semiconductorsubstrate 1S can be defined as a position at which the dopingconcentration decreases by half (½) of the concentration of thesemiconductor substrate 1S as described referring to FIG. 7. Theimpurity profile in the body diode BD is thus described. In the bodydiode BD formation region, the boundary between the epitaxial layer epi1and epitaxial layer epi2 which is one of the characteristics ofEmbodiment 1 has no direct relationship.

Embodiment 1 is characterized by that the boundary between the epitaxiallayer epi1 and the epitaxial layer epi2 is formed in a region equal toor shallower than the depth of the trench T and the boundary between theepitaxial layer epi1 and the epitaxial layer epi2 should be definedclearly. From this viewpoint, as illustrated in FIG. 7, an impurityprofile of the Schottky barrier diode SBD in which the boundary betweenthe epitaxial layer epi1 and the epitaxial layer epi2 appears directlyis important and the boundary between the epitaxial layer epi1 and theepitaxial layer epi2 is defined clearly by using this impurity profile.On the other hand, the impurity profile of the body diode BD illustratedin FIG. 9 has no direct relationship with the characteristic ofEmbodiment 1 but is shown in FIG. 9 for reference.

As described above, Embodiment 1 is characterized by that two epitaxiallayers, that is, the epitaxial layer epi1 having a high dopingconcentration and the epitaxial layer epi2 having a low dopingconcentration are formed over the semiconductor substrate 1S and theboundary between the epitaxial layer epi1 and the epitaxial layer epi2is formed in a region equal in depth to the bottom portion of the trenchT or shallower than the bottom portion of the trench T. As alreadydescribed above, such a configuration enables to simultaneously realizesuppression of a drastic increase in the on-resistance of the powerMISFET and improvement in the avalanche breakdown voltage in theSchottky barrier diode SBD, which are in a trade-off relationship.Simulation is performed to confirm such an effect. The simulation willhereinafter be described.

The first simulation is performed based on, for example, the structure,as illustrated in FIG. 6, obtained by forming an epitaxial layer epi1having a high doping concentration over a semiconductor substrate 1S andthen forming an epitaxial layer epi2 over the epitaxial layer epi1having a high doping concentration. With this structure, the powerMISFET and the Schottky barrier diode SBD are formed. The object of thefirst simulation is to study the relationship between an avalanchebreakdown voltage of the Schottky barrier diode SBD and an on-resistanceof the power MISFET while changing the resistivity ρepi2 and the filmthickness tepi2 of the epitaxial layer epi2 (low doping concentration)formed as an upper layer. This simulation is performed while setting theresistivity of the first epitaxial layer epi1 at 0.3 Ocm. Theresistivity is similar to that of an epitaxial layer composed of only asingle layer formed over the semiconductor substrate 1S (conventionalstructure). Evaluation is made while fixing the total film thickness ofthe tepi1, that is, the thickness of the epitaxial layer epi1 and thetepi2, that is, the thickness of the epitaxial layer epi2 at 3.5 μm.

FIG. 10 is a graph showing the relationship between a depth from thesurface of the epitaxial layer epi2 and a doping concentration afterformation of the epitaxial layer epi1 and the epitaxial layer epi2 overthe semiconductor substrate 1S. It illustrates the semiconductorsubstrate 1S having thereover only the epitaxial layer epi1 and theepitaxial layer epi2. As illustrated in FIG. 10, the resistivity ρepi2of the epitaxial layer epi2 is changed from 0.3 Ocm, 0.8 Ocm, 1.0 Ocm,1.2 Ocm, to 1.4 Ocm. In this case, as FIG. 10 shows, with an increase inthe resistivity ρepi2, the doping concentration becomes low. In otherwords, with a decrease in the resistivity ρepi2, the dopingconcentration becomes high. In FIG. 10, the boundary between theepitaxial layer epi2 and the epitaxial layer epi1 is present at 1.0 μmdeep from the surface of the epitaxial layer epi2 and the trench has adepth of 0.8 μm. In view of this, after only the epitaxial layer epi1and the epitaxial layer epi2 are formed over the semiconductor substrate1S (the state of FIG. 10), the boundary between the epitaxial layer epi2and the epitaxial layer epi1 is present at a position deeper than thedepth of the trench.

FIG. 11 is a graph showing the relationship between a depth from thesurface of the epitaxial layer epi2 and a doping concentration aftercompletion of a semiconductor device having a power MISFET and aSchottky barrier diode SBD. In other words, FIG. 11 is a graph showingthe relationship between the depth from the surface of the epitaxiallayer epi2 and the doping concentration after various heat treatments.

As illustrated in FIG. 11, the boundary between the epitaxial layer epi2and the epitaxial layer epi1 shows a mild change due to diffusion ofimpurities by the heat treatment. It has revealed that the boundarybetween the epitaxial layer epi2 and the epitaxial layer epi1 transfersto a region shallower than that shown in FIG. 10 and is present in aregion shallower than the depth (0.8 μm) of the trench.

Even if the boundary between the epitaxial layer epi2 and the epitaxiallayer epi1 shows a mild change due to diffusion of impurities by theheat treatment, the doping concentration decreases with an increase inthe resistivity ρepi2. In other words, even after completion of thesemiconductor device, the doping concentration on the surface of theepitaxial layer epi2 can be reduced as the resistivity ρepi2 becomeshigher. This suggests that as the resistivity ρepi2 of the epitaxiallayer epi2 becomes higher, the avalanche breakdown voltage of theSchottky barrier diode SBD formed over the surface of the epitaxiallayer epi2 can be made greater.

FIG. 12 is a graph showing the relationship between a depth from thesurface of the epitaxial layer epi2 in the power MISFET formation regionand a doping concentration. As is apparent from FIG. 12, the dopingconcentration decreases even in a region deeper than the trench depthwhen the resistivity ρepi2 is 0.8 Ocm, 1.0 Ocm, 1.2 Ocm, or 1.4 Ocmcompared with when the resistivity ρepi2 is 0.3 Ocm. This means thatwhen the resistivity ρepi2 of the epitaxial layer epi2 is 0.3 Ocm, theresistivity ρepi1 of the epitaxial layer epi1 is equal to theresistivity ρepi2 of the epitaxial layer epi2. This structure issubstantially similar to the conventional structure composed of a singleepitaxial layer having a resistivity of 0.3 Ocm. When the resistivityρepi2 of the epitaxial layer epi2 is 0.8 Ocm, 1.0 Ocm, 1.2 Ocm, or 1.4Ocm, the doping concentration becomes lower than that of theconventional structure even in a region deeper than the depth of thetrench. Even in the first simulation, the epitaxial layer epi1 having aresistivity equal to that of the conventional structure is formed in aregion deeper than the depth of the trench, but when the resistivityρepi2 of the epitaxial layer epi2 is 0.8 Ocm, 1.0 Ocm, 1.2 Ocm, or 1.4Ocm, the doping concentration becomes lower than that of theconventional structure in a region deeper than the depth of the trench.This suggests that an increase in the resistivity ρepi2 of the epitaxiallayer epi2 leads to an increase in the on-resistance of the power MISFETeven if the resistivity ρepi1 of the epitaxial layer epi1 is equal tothat of the conventional structure. In other words, even if, aftercompletion of the semiconductor device having the epitaxial layer epi2and the epitaxial layer epi1 stacked one after another, the boundarybetween the epitaxial layer epi1 and the epitaxial layer epi2 is presentin a region shallower than the depth of the trench, the dopingconcentration decreases in a region deeper than the depth of the trench.A decrease in the doping concentration of the epitaxial layer epi1 ispresumed to occur because when the doping concentration of the epitaxiallayer epi2 is reduced, impurity diffusion to the side of the epitaxiallayer epi2 occurs from the heavily-doped epitaxial layer epi1 ratherthan from the epitaxial layer epi2. This suggests that in order todecrease the doping concentration of the epitaxial layer epi2, thedoping concentration of the epitaxial layer epi1 should be set higherthan that of the conventional structure.

The above-described first simulation is repeated while changing thethickness tepi2 of the epitaxial layer epi2. The results are shownbelow. FIG. 13 is a graph showing the relationship between a thicknesstepi2 of the epitaxial layer epi2 and an avalanche breakdown voltage ofthe Schottky barrier diode SBD and between a thickness tepi2 of theepitaxial layer epi2 and an avalanche breakdown voltage of the powerMISFET. It should be noted that FIG. 13 simultaneously shows therelationships when the resistivities ρepi2 of the epitaxial layer epi2are 0.8 Ocm, 1.0 Ocm, 1.2 Ocm, and 1.4 Ocm, respectively. In FIG. 13,the thickness tepi2 of the epitaxial layer epi2 is plotted on theabscissa, while the avalanche breakdown voltage is plotted on theordinate. A solid line in the graph indicates the Schottky barrier diodeSBD and a broken line in the graph indicates the power MISFET. Thethickness tepi2 of the epitaxial layer epi2 is not a film thickness uponcompletion of the semiconductor device but that upon formation of theepitaxial layer epi2.

As illustrated in FIG. 13, the avalanche breakdown voltage of theSchottky barrier diode SBD becomes greater than the avalanche breakdownvoltage of the power MISFET at the thickness tepi2 of the epitaxiallayer epi2 exceeding 1.0 μm. It is therefore at least necessary toadjust the thickness tepi2 of the epitaxial layer epi2 to about 1 μm inorder to make the avalanche breakdown voltage of the Schottky barrierdiode SBD higher than the avalanche breakdown voltage of the powerMISFET.

FIG. 14 is a graph showing the relationship between a thickness tepi2 ofthe epitaxial layer epi2 and a relative on-resistance of the powerMISFET. The thickness tepi2 of the epitaxial layer epi2 is plotted onthe abscissa of FIG. 14, while the relative on-resistance of the powerMISFET is plotted on the ordinate of FIG. 14. The on-resistance of thepower MISFET is a value relative to the on-resistance of theconventional structure composed of a single epitaxial layer having aresistivity of 0.3 Ocm. FIG. 14 simultaneously shows the relationshipswhen the resistivities ρepi2 of the epitaxial layer epi2 are 0.8 Ocm,1.0 Ocm, 1.2 Ocm, and 1.4 Ocm, respectively.

As derived from FIG. 13, the thickness tepi2 of the epitaxial layer epi2should be set at about 1 μm in order to make the avalanche breakdownvoltage of the Schottky barrier diode SBD greater than the avalanchebreakdown voltage of the power MISFET. Application of this result toFIG. 14 reveals that the on-resistance at this time is higher than theon-resistance of the conventional structure. More specifically, theon-resistance shows a 15% to 20% increase compared with that of theconventional structure. It is therefore understood that under theconditions of the first simulation, the avalanche breakdown voltage ofthe Schottky barrier diode SBD can be raised, but a drastic increase ofthe on-resistance cannot be suppressed.

As described in FIG. 12, even when the boundary between the epitaxiallayer epi1 and the epitaxial layer epi2 after completion of thesemiconductor device by stacking the epitaxial layer epi2 over theepitaxial layer epi1 is present in a region shallower than the depth ofthe trench, the doping concentration of the epitaxial layer epi1 reducesin a region deeper than the depth of the trench. It is presumed thatwhen the doping concentration of the epitaxial layer epi2 is reduced,diffusion of impurities from the epitaxial layer epi1 having a higherconcentration than that of the epitaxial layer epi2 occurs by heattreatment and a reduction in the doping concentration of the epitaxiallayer epi1 occurs. This suggests that the doping concentration of theepitaxial layer epi1 formed below the epitaxial layer epi2 should bemade higher than that of the conventional structure in order to reducethe doping concentration of the epitaxial layer epi2. In view of this, asecond simulation is performed. The second simulation will hereinafterbe described.

Based on the results of the first simulation, the resistivity of thefirst epitaxial layer epi1 is changed from resistivity ρepi1 of 0.3 Ocmto resistivity ρepi1 of 0.2 Ocm in the second simulation. This meansthat the doping concentration of the first epitaxial layer epi1 is madehigher than that of the first simulation. Conditions other than theabove-described one are similar to those of the first simulation. Forexample, the total thickness of the thickness tepi1 of the epitaxiallayer epi1 and the thickness tepi2 of the epitaxial layer epi2 is fixedat 3.5 μm.

FIG. 15 is a graph showing the relationship between a depth from thesurface of the epitaxial layer epi2 and a doping concentration afterformation of the epitaxial layer epi1 and the epitaxial layer epi2 overthe semiconductor substrate 1S. In short, this graph shows thesemiconductor substrate 1S having thereover only the epitaxial layerepi1 and the epitaxial layer epi2. As shown in FIG. 15, the resistivityof the epitaxial layer epi2 is varied from the resistivity ρepi2 of from0.2 Ocm, 0.8 Ocm, 1.0 Ocm, 1.2 Ocm, and 1.4 Ocm. As is apparent fromFIG. 15, the higher the resistivity ρepi2, the lower the dopingconcentration, which is similar to the first simulation shown in FIG.10.

Also in the state shown by FIG. 15, similar to FIG. 10, the boundarybetween the epitaxial layer epi2 and the epitaxial layer epi1 is present1.0 μm deep from the surface of the epitaxial layer epi2. The depth ofthe trench is 0.8 μm. In consideration of this, the boundary between theepitaxial layer epi2 and the epitaxial layer epi1 is present in a regiondeeper than the depth of the trench when only the epitaxial layer epi1and the epitaxial layer epi2 are formed over the semiconductor substrate1S (the state of FIG. 15).

FIG. 16 is a graph showing the relationship between a depth from thesurface of the epitaxial layer epi2 and a doping concentration aftercompletion of the semiconductor device having a power MISFET and aSchottky barrier diode SBD. In short, FIG. 16 is a graph showing therelationship between a depth from the surface of the epitaxial layerepi2 and a doping concentration after various heat treatment steps.

As shown in FIG. 16, at the boundary between the epitaxial layer epi2and the epitaxial layer epi1, the doping concentration shows a gradualchange due to diffusion of impurities by the heat treatment. Theboundary between the epitaxial layer epi2 and the epitaxial layer epi1transfers to a region shallower than that shown in FIG. 15 and ispresent in a region shallower than the depth (0.8 μm) of the trench.

Even after completion of the semiconductor device, the dopingconcentration in the surface of the epitaxial layer epi2 can be madelower as the resistivity ρepi2 becomes higher. This suggests that as theresistivity ρepi2 of the epitaxial layer epi2 becomes higher, theavalanche breakdown voltage of the Schottky barrier diode SBD formed onthe surface of the epitaxial layer epi2 can be made higher.

FIG. 17 is a graph showing the depth from the surface of the epitaxiallayer epi2 and the doping concentration in the power MISFET formationregion. In FIG. 17, a graph plotted with triangles shows the results ofthe second simulation. In the graph (line) plotted with triangles, theresistivity ρepi1 of the first epitaxial layer epi1 is 0.2 Ocm and theresistivity ρepi2 of the second epitaxial layer epi2 is 1.0 Ocm. At thistime, the thickness tepi1 of the epitaxial layer epi1 is 2.5 μm and thethickness tepi2 of the second epitaxial layer is 1.0 μm.

As illustrated in FIG. 17, in a region deeper than the depth (0.8 μm) ofthe trench, the graph showing the results of the second simulation andplotted with triangles shows a higher doping concentration than thegraph showing the conventional structure and plotted with solid circles.The conventional structure employs a single epitaxial layer and thissingle epitaxial layer has a resistivity of 0.3 Ocm. This suggests thatthe resistance in a region deeper than the trench and will serve as adrift region of the power MISFET can be made lower than that of theconventional structure. The graph plotted with blank circles shows theresults of the first simulation. In this case, similar to FIG. 12, thedoping concentration becomes lower than that of the conventionalstructure in a drift region deeper than the trench. According to theresults of the first simulation, the resistance therefore becomes higherthan that of the conventional structure. It is therefore expected thatin the second simulation, a drastic increase in the on-resistance of thepower MISFET can be suppressed by changing the resistivity ρepi1 of thefirst epitaxial layer epi1 from 0.3 Ocm to 0.2 Ocm.

Repetition of the second simulation while changing the thickness tepi2of the epitaxial layer epi2 results in the following. FIG. 18 is a graphshowing the relationship between a thickness tepi2 of the epitaxiallayer epi2 and an avalanche breakdown voltage of the Schottky barrierdiode SBD and the relationship between a thickness tepi2 of theepitaxial layer epi2 and an avalanche breakdown voltage of the powerMISFET. FIG. 18 shows simultaneously the relationships when theresistivities ρepi2 of the epitaxial layer epi2 are 0.8 Ocm, 1.0 Ocm,1.2 Ocm, and 1.4 Ocm, respectively. The thickness tepi2 of the epitaxiallayer epi2 is plotted on the abscissa of FIG. 18, while the avalanchebreakdown voltage is plotted on the ordinate of FIG. 18. A solid line inthe graph indicates the Schottky barrier diode SBD and a broken line inthe graph indicates the power MISFET. The thickness tepi2 of theepitaxial layer epi2 is not a film thickness upon completion of thesemiconductor device but that upon formation of the epitaxial layerepi2.

As illustrated in FIG. 18, the avalanche breakdown voltage of theSchottky barrier diode SBD becomes higher than the avalanche breakdownvoltage of the power MISFET at the thickness tepi2 of the epitaxiallayer epi2 exceeding 1.0 μm. It is therefore possible to adjust thethickness tepi2 of the epitaxial layer epi2 to about 1.2 μm in order tomake the avalanche breakdown voltage of the Schottky barrier diode SBDhigher than the avalanche breakdown voltage of the power MISFET.

FIG. 19 is a graph showing the relationship between a thickness tepi2 ofthe epitaxial layer epi2 and a relative on-resistance of the powerMISFET. The thickness tepi2 of the epitaxial layer epi2 is plotted onthe abscissa of FIG. 19, while the relative on-resistance of the powerMISFET is plotted on the ordinate of FIG. 19. The on-resistance of thepower MISFET is a value relative to the on-resistance of theconventional structure composed of a single epitaxial layer having aresistivity of 0.3 Ocm. FIG. 19 shows simultaneously the relationshipswhen the resistivities of the epitaxial layer epi2 are 0.8 Ocm, 1.0 Ocm,1.2 Ocm, and 1.4 Ocm, respectively.

As derived from FIG. 18, it is presumed to set the thickness tepi2 ofthe epitaxial layer epi2 to about 1.2 μm in order to make the avalanchebreakdown voltage of the Schottky barrier diode SBD higher than theavalanche breakdown voltage of the power MISFET. Application of thisresult to FIG. 19 reveals that although the on-resistance at this timeis higher than the on-resistance of the conventional structure, anincrease in the on-resistance can be suppressed at from about 5% to 10%compared with that of the conventional structure. It is thereforeunderstood that under the conditions of the second simulation, theavalanche breakdown voltage of the Schottky barrier diode SBD can beraised and a drastic increase of the on-resistance can be suppressed.

Based on the results of the second simulation, by reducing theresistivity ρepi1 of the first epitaxial layer epi1 to 0.2 Ocm(corresponding to an increase in the doping concentration) andoptimizing a ratio of the second epitaxial layer epi2 to the firstepitaxial layer epi2 (tepi2/tepi1=1.2 μm/2.3 μm), the resistivity ρepi2of the second epitaxial layer epi2 can be adjusted to from 0.8 to 1.4Ocm. This enables to make the avalanche breakdown voltage of theSchottky barrier diode SBD higher than the avalanche breakdown voltageof the power MISFET and to suppress an increase in the on-resistance ofthe power MISFET to from about 5 to 10%.

As the results of the second simulation suggest, the dopingconcentration of the second epitaxial layer epi2 can be reduced andtherefore, the field intensity on the surface of the epitaxial layerepi2 where a Schottky junction is to be formed can be relaxed, whichwill hereinafter be described, referring to FIG. 20.

FIG. 20 is a graph showing the relationship between a depth from thesurface of the epitaxial layer epi2 and a field intensity. In FIG. 20,the depth from the surface of the epitaxial layer epi2 is plotted on theabscissa, while the field intensity is plotted on the ordinate. Thegraph plotted with solid circles shows the conventional structure usinga single epitaxial layer, while the graph plotted with squares shows thestructure of the second simulation. In the conventional structure, theepitaxial layer has a thickness of 3.5 μm and has a resistivity ρepi1 of0.3 Ocm. In the structure of the second simulation, on the other hand,the first epitaxial layer epi1 has a thickness of 2.3 μm and aresistivity ρepi1 of 0.2 Ocm and the second epitaxial layer epi2 has athickness of 1.2 μm and a resistivity ρepi2 of 1.0 Ocm.

As illustrated in FIG. 20, in the conventional structure (solidcircles), the field intensity on the surface where a Schottky junctionis formed exceeds 4.0E+05 (V/cm). In the structure of the secondsimulation, on the other hand, the field intensity on the surface of theepitaxial layer epi2 where a Schottky junction is formed is relaxed toabout 3.2E+05 (V/cm). This suggests that the avalanche breakdown voltageof the Schottky barrier diode SBD can be made higher in the structure ofthe second simulation than in the conventional structure. In otherwords, in the structure of the second simulation, the Schottky barrierdiode can have an improved breakdown voltage.

Based on the results of the second simulation, it is possible toquantitatively predict that the semiconductor device of Embodiment 1 canachieve improvement in the avalanche breakdown voltage of the Schottkybarrier diode SBD and suppression of a drastic increase in theon-resistance of the power MISFET. Based on the second simulation, asemiconductor device having a Schottky barrier diode SBD and a powerMISFET over one semiconductor chip (semiconductor substrate) and havingthe characteristics of Embodiment 1 was manufactured. It is verifiedthat a DC/DC converter using the resulting semiconductor device canreduce a circuit loss during dead time.

FIG. 21 is a graph showing the relationship between a forward voltage VFand a forward current IF in a structure in which a Schottky barrierdiode SBD and a power MISFET are formed over one semiconductor substrateand they are coupled to each other in parallel. For comparison, FIG. 21includes a graph showing the relationship between a forward voltage VFand a forward current IF in a structure without not equipped with aSchottky barrier diode. The structure having no Schottky barrier diodeSBD is a structure in which a forward current is provided for a bodydiode parasitically formed in the power MISFET. In FIG. 21, a forwardcurrent IF is plotted on the ordinate, while a drop of a forward voltageVF is plotted on the abscissa.

As illustrated in FIG. 21, when, for example, a forward current IF flowsonly at 1.0E−0.3 (A), a drop of a forward voltage VF is about 0.2V in astructure equipped with the Schottky barrier diode SBD. On the otherhand, in a structure not equipped with the Schottky barrier diode SBD, adrop of the forward voltage VF is even about 0.5V. This means that whenthe forward current IF is equal, a drop of the forward voltage VFbecomes smaller than in the structure equipped with the Schottky barrierdiode SBD. This suggests that a loss energy becomes smaller in thestructure equipped with the Schottky barrier diode SBD than in thestructure not equipped with the Schottky barrier diode SBD. Applicationof the semiconductor device (structure equipped with the Schottkybarrier diode SBD) of Embodiment 1 to a DC/DC converter enables toreduce a circuit loss during a dead time, resulting in reduction in thepower consumption of the DC/DC converter.

In addition, the semiconductor device according to Embodiment 1 enablesto improve the breakdown voltage of the Schottky barrier diode SBD. Thisadvantage will hereinafter be described. FIG. 22 is a graph showing therelationship between a breakdown voltage VDSS (reverse voltage) and aleakage current IDSS. More specifically, FIG. 22 shows the relationshipbetween a breakdown voltage VDSS (reverse voltage) and a leakage currentIDSS both in the semiconductor device of Embodiment 1 having, over onesemiconductor substrate thereof, a Schottky barrier diode SBD and apower MISFET arranged in parallel and a structure not equipped with aSchottky barrier diode SBD. In FIG. 22, the breakdown voltage VDSS isplotted on the abscissa and the leakage current is plotted on theordinate.

As is apparent from FIG. 22, the semiconductor device (having astructure equipped with the Schottky barrier diode SBD) according toEmbodiment 1 has a breakdown voltage VDSS (about 33V) similar to thebreakdown voltage (VDSS) of the structure (body diode) not equipped witha Schottky barrier diode SBD. In other words, in a structure obtained byforming a power MISFET and a Schottky barrier diode SBD over a singleepitaxial layer, the Schottky barrier diode SBD has inevitably a reducedbreakdown voltage (avalanche breakdown voltage). According to Embodiment1, however, two epitaxial layers, that is, the epitaxial layer epi1having a high doping concentration and the epitaxial layer epi2 having alow doping concentration are formed over the semiconductor substrate 1Sand the boundary between the epitaxial layer epi1 and the epitaxiallayer epi2 is formed in a region as deep as the bottom portion of thetrench T or shallower than the bottom portion of the trench T. TheSchottky barrier diode SBD is therefore formed using a Schottky junctionbetween the lightly-doped epitaxial layer epi2 and the first metal film6. As illustrated in FIG. 22, the breakdown voltage in Embodiment 1 canbe kept equal to that of the structure (body diode) not equipped withthe Schottky barrier diode.

With regards to the characteristics of the Schottky barrier diode SBD,as illustrated in FIGS. 21 and 22, a drop of the forward voltage VF canbe reduced, but the leakage current increases when a reverse voltage isapplied. Although the leakage current of the Schottky barrier diode isgreater than that of the body diode (a structure not equipped with aSchottky barrier diode SBD) using a pn junction, it does notsubstantially affect the practical use.

The Schottky barrier diode has an increased leakage current IDSS when adrop of the forward voltage VF is reduced. This means that the area ofthe Schottky barrier diode SBD should be increased in order to reduce adrop of the forward voltage VF. The increase in the area of the Schottkybarrier diode SBD however leads to an increase in the leakage currentIDSS. Between the drop of the forward voltage VF and the leakage currentIDSS, there is therefore a trade-off relationship from the standpoint ofthe area of the Schottky barrier diode SBD. The magnitude of the leakagecurrent IDSS however depends on not only the area of the Schottkybarrier diode SBD but also the kind of a metal film forming the Schottkyjunction.

For example, FIG. 23 illustrates a band structure of a metal film and asemiconductor layer forming a Schottky junction. In FIG. 23, φbnrepresents a Schottky barrier height and the magnitude of the leakagecurrent IDSS varies, depending on the Schottky barrier height φbn. Atthis time, the Schottky barrier height φbn varies, depending on the kindof the metal film. The magnitude of the leakage current IDSS cantherefore be adjusted by changing the kind of a metal film used for theformation of a Schottky junction. More specifically, with an increase inthe Schottky barrier height φbn, the leakage current IDSS can bereduced. In other words, with a decrease in the Schottky barrier heightφbn, the leakage current IDSS increases.

This suggests that a metal film having a relatively low Schottky barrierheight φbn may be used when some increase in the leakage current IDSS isallowed, while a metal film having a relatively high Schottky barrierheight φbn may be used when the leakage current IDSS should bedecreased. For example, a titanium tungsten (TiW) film has a Schottkybarrier height φbn of 0.65 eV and a titanium nitride/titanium (TiN/Ti)film has a Schottky barrier height φbn of 0.60 eV. This means that useof a titanium tungsten film as the metal film can reduce the leakagecurrent IDSS. Use of a titanium nitride/titanium film as the metal film,on the other hand, provides some increase in the leakage current IDSS.

Thus, the leakage current IDSS increases by expanding the area of theSchottky barrier diode SBD in order to reduce a drop of the forwardvoltage VF of the Schottky barrier diode SBD. The increase in theleakage current IDSS can however be suppressed by selecting, as themetal film forming a Schottky junction, a material having a highSchottky barrier height φbn such as a titanium tungsten film. If someincrease in the leakage current is allowed, on the other hand, amaterial having a low Schottky barrier height φbn such as titaniumnitride/titanium film can be selected. A cobalt (Co) film popularly usedin the process (salicide) of simultaneously forming a silicide over agate electrode and a diffusion layer (such as source region) has aSchottky barrier height φbn of from 0.64 to 0.68 eV. Use of this filmenables to make the leakage current IDSS smaller than that when titaniumis used as the metal film.

A manufacturing method of the semiconductor device according toEmbodiment 1 will hereinafter be described referring to some drawings.

As illustrated in FIG. 24, a semiconductor substrate 1S doped with ntype impurities such as phosphorus or arsenic is prepared. FIG. 24illustrates power MISFET formation regions and an SBD formation region(Schottky barrier diode SBD formation region) of the semiconductorsubstrate 1S. Described specifically, the SBD formation region issandwiched between the power MISFET formation regions formed on bothsides thereof.

As illustrated in FIG. 25, an epitaxial layer epi1 is then formed overthe semiconductor substrate 1S, followed by the formation of anepitaxial layer epi2 over the epitaxial layer epi1. The epitaxial layerepi1 and the epitaxial layer epi2 are each formed by the epitaxialgrowth, but they are different from each other in the amount of n typeimpurities introduced therein. More specifically, the n type impuritiesare introduced heavily into the epitaxial layer epi1 formed as a firstlayer, while the n type impurities are introduced lightly into theepitaxial layer epi2 formed as the second layer. In Embodiment 1, thesemiconductor substrate 1S, the epitaxial layer epi1, and the epitaxiallayer epi2 will hereinafter be called “multilayer substrate”,collectively.

Another method for forming the multilayer substrate will next bedescribed. As illustrated in FIG. 26, a lightly doped epitaxial layerepi2 is formed over the semiconductor substrate 1S. The lightly dopedepitaxial layer epi2 is formed, for example, by the epitaxial growth.Then, as illustrated in FIG. 27, n type impurities such as phosphorusare introduced into a deep region contiguous to the semiconductorsubstrate 1S by employing ion implantation for the entire surface of thesemiconductor substrate 1S. This enables to form a heavily dopedepitaxial layer epi1 having a higher doping concentration than that ofthe epitaxial layer epi2 between the semiconductor substrate 1S and theepitaxial layer epi2. As a result, a multilayer substrate having, on thesemiconductor substrate 1S thereof, the heavily doped epitaxial layerepi1 and the lightly doped epitaxial layer epi1 can be formed.

A further method for forming the multilayer substrate will next bedescribed. As illustrated in FIG. 28, a heavily doped epitaxial layer (ntype semiconductor layer) epi1 is formed over the semiconductorsubstrate 1S. This heavily doped epitaxial layer epi1 can be formedusing, for example, the epitaxial growth. Then, as illustrated in FIG.29, p type impurities such as boron are introduced into a shallow regionof the epitaxial layer epi1 by using ion implantation for the entiresurface of the semiconductor substrate 1S. This enables to form anepitaxial layer epi2 having a low doping concentration than that of theepitaxial layer epi1 in the shallow region of the epitaxial layer epi1.This means that introduction of p type impurities having a conductivitytype opposite to that of the n type impurities into the shallow regionof the epitaxial layer epi1 offsets the n type impurities of theepitaxial layer epi1 into which the p type impurities have beenintroduced, whereby the concentration of the n type impurities becomeslow. As a result, a multilayer substrate having, over the semiconductorsubstrate 1S thereof, the heavily doped epitaxial layer epi1 and thelightly doped epitaxial layer epi2 can be formed.

As described above, there are three methods for forming a multilayersubstrate. Of these, the first one is the most inexpensive method. Thesecond method and the third method are also usable, but the second oneis preferred, because the doping concentration of the lightly dopedepitaxial layer epi2 can be made uniform more easily in the secondmethod. The lightly doped epitaxial layer epi2 is a layer to be used forforming a Schottky barrier diode and a doping concentration should berealized as designed in order to ensure the breakdown voltage of theSchottky barrier diode. In the second method, the lightly dopedepitaxial layer epi2 is formed by the epitaxial growth so that itsdoping concentration tends to be constant with less variation. In thethird method, on the other hand, the lightly doped epitaxial layer epi2is formed by ion implantation so that the doping concentration of theepitaxial layer epi2 tends to vary.

Steps after the formation of the multilayer substrate will hereinafterbe described. As illustrated in FIG. 30, a silicon oxide film 2 isformed over the epitaxial layer epi2. This silicon oxide film 2 can beformed, for example, by wet oxidation at about 1000° C. By the heattreatment for forming this silicon oxide film 2, impurity diffusionoccurs from the heavily doped epitaxial layer epi1 to the lightly dopedepitaxial layer epi2. This means that rise of the impurities from theepitaxial layer epi1 leads to a decrease in the thickness of theepitaxial layer epi2. In addition, it flattens the concentrationgradient of the impurities at the boundary between the epitaxial layerepi1 and the epitaxial layer epi2. In Embodiment 1, by the heattreatment in the step of forming the silicon oxide film 2 illustrated inFIG. 30, impurities are diffused from the epitaxial layer epi1 to theepitaxial layer epi2, but a similar diffusion phenomenon also occurs inanother heat treatment step. In Embodiment 1, however, a change of theposition of the boundary between the epitaxial layer epi1 and theepitaxial layer epi2 due to the influence of another heat treatment stepis omitted.

As illustrated in FIG. 31, the silicon oxide film 2 is then patternedusing photolithography and etching. The patterning of the silicon oxidefilm 2 is performed so as to open therein a trench formation region. Byetching with the patterned silicon oxide film 2 as a mask, a trench T isformed in the multilayer substrate. More specifically, the trench Tpenetrating through the lightly doped epitaxial layer epi2 and reachingthe heavily doped epitaxial layer epi1 is formed. As a result, theboundary between the epitaxial layer epi1 and the epitaxial layer epi2can be located at a position equal to or shallower than the depth of thetrench T. FIG. 32 shows that the boundary between the epitaxial layerepi1 and the epitaxial layer epi2 is located at a position shallowerthan the depth of the trench T.

The trench T is formed in the power MISFET formation regions. The SBDformation region is sandwiched between the trenches T formed in the endportion of the power MISFET formation regions formed on both sides ofthe SBD formation region.

As illustrated in FIG. 33, a gate insulating film GOX is then formed onthe inner wall of the trench T. The gate insulating film GOX is made of,for example, a silicon oxide film and can be formed using, for example,thermal oxidation. The gate insulating film GOX is not limited to asilicon oxide film, but various films may be employed. For example, thegate insulating film GOX may be a silicon oxynitride (SiON) film. Thismeans that nitrogen may be segregated at the interface between the gateinsulating film GOX and the trench T. The silicon oxynitride film ismore effective than the silicon oxide film in suppressing generation ofan interface state in the film or reducing an electron trap. The gateinsulating film GOX made of the silicon oxynitride film can thereforehave improved hot carrier resistance and improved insulation resistance.In addition, the silicon oxynitride film is more resistant to impuritypenetration therethrough than the silicon oxide film. Use of the siliconoxynitride film as the gate insulating film GOX therefore enables tosuppress variations in the threshold voltage which may otherwise occurby the diffusion of impurities contained in a gate electrode to the sideof the multilayer substrate. The silicon oxynitride film is formed, forexample, by heat treating the multilayer substrate in a nitrogenousatmosphere such as NO, NO₂ or NH₃. Similar effects are available byforming the gate insulating film GOX made of a silicon oxide film on theinner wall of the trench T and then, heat treating the multilayersubstrate in a nitrogenous atmosphere to segregate nitrogen at theinterface between the gate insulating film GOX and the trench T.

Alternatively, the gate insulating film GOX may be made of a highdielectric film having a higher dielectric constant than that of asilicon oxide film. As the gate insulating film GOX, a silicon oxidefilm is conventionally used from the standpoint that it has highinsulation resistance and excellent electrical/physical stability at asilicon-silicon oxide interface. With the miniaturization of elements,however, the gate insulating film GOX is required to be ultrathin. Whena thin silicon oxide film is used as the gate insulating film GOX,however, electrons running through the channel of a MISFET tunnel abarrier formed by the silicon oxide film and flow into the gateelectrode. Thus, a so-called tunneling current inevitably occurs.

To overcome the above problem, a high dielectric film using a materialhaving a higher dielectric constant than that of the silicon oxide filmand therefore capable of having an increased physical thickness withoutchanging the capacitance has come to be used. Use of such a highdielectric film enables to reduce a leakage current because it canincrease the physical film thickness without changing the capacitance.

For example, a hafnium oxide film (HfO₂ film), one of hafnium oxides, isused as the high dielectric film. The hafnium oxide film may be replacedby another hafnium insulating film such as hafnium aluminate film, HfONfilm (hafnium oxynitride film), HfSiO film (hafnium silicate film),HfSiON film (hafnium silicon oxynitride film), or HfAlO film. A hafniuminsulating film obtained by introducing, into the above-describedhafnium insulating film, tantalum oxide, niobium oxide, titanium oxide,zirconium oxide, lanthanum oxide or yttrium oxide is also usable. Thesehafnium insulating films have, similar to a hafnium oxide film, a higherdielectric constant than a silicon oxide film or silicon oxynitride filmso that they can exhibit a similar effect to the hafnium oxide film.

As illustrated in FIG. 34, a polysilicon film 3 is formed over thesilicon oxide film 2. This polysilicon film 3 is formed so as to fillthe inside of the trench T therewith. The polysilicon film 3 has beendoped with n type impurities such as phosphorus (P) or arsenic (As) andcan be formed, for example, by CVD (Chemical Vapor Deposition). Then, asillustrated in FIG. 35, the polysilicon film 3 formed over the siliconoxide film 2 is etched back and removed by overall dry etching, wherebya gate electrode G having a structure in which the polysilicon film 3has been filled in the trench T is formed.

As illustrated in FIG. 36, the silicon oxide film 2 is then removed, forexample, by dry etching. As illustrated in FIG. 37, a resist R1 isformed by application onto the multilayer substrate and the resultingresist film R1 is subjected to exposure/development to pattern theresist film R1. This patterning is performed so as to cover the centerportion of the SBD formation region. Then, by ion implantation with thepatterned resist film R1 as a mask, p type impurities are introducedinto the multilayer substrate, whereby a channel region CH which is a ptype semiconductor region is formed in the power MISFET formationregion. On the other hand, a p ring PR which is a p type semiconductorregion is formed in the end portion of the SBD formation region notcovered with the resist R1. Thus, in Embodiment 1, the channel region CHin the power MISFET formation region and the p ring PR in the endportion of the SBD formation region are formed in one step. The channelregion CH and the p ring PR region have therefore an equal dopingconcentration.

The channel region CH and the p ring PR are formed in a region shallowerthan the depth of the trench T but the p type impurities are introducedto completely offset the epitaxial layer epi2 which is an n typesemiconductor region. This means that the channel region CH and the pring PR are formed so as to reach to a region deeper than the boundarybetween the epitaxial layer epi1 and the epitaxial layer epi2. As aresult, the epitaxial layer epi2 completely disappears in the powerMISFET formation region.

After removal of the patterned resist film R1, a resist film R2 isformed by application onto the multilayer substrate as illustrated inFIG. 38. The resulting resist film R2 is subjected toexposure/development treatment to pattern the resist film R2. The resistfilm R2 is patterned so as to cover the SBD formation region therewith.Then, by ion implantation with the patterned resist film R2 as a mask, asource region SR which is an n type semiconductor region is formed overthe channel region CH of the power MISFET formation region. This sourceregion SR is contiguous to the trench T.

As illustrated in FIG. 39, after removal of the patterned resist filmR2, an interlayer insulating film IL is formed over the multilayersubstrate. The interlayer insulating film IL is made of, for example, aPSG (Phospho Silicate Glass) film. As illustrated in FIG. 40, a contacthole C1 and a contact hole C2 are formed in the interlayer insulatingfilm IL by using photolithography and etching. The contact hole C1 isformed in the power MISFET formation region, while the contact hole C2is formed in the SBD formation region.

As illustrated in FIG. 41, the contact hole C1 and the contact hole C2formed in the interlayer insulating film IL are extended to the insideof the multilayer substrate. Described specifically, in the power MISFETformation region, the contact hole C1 is formed so that it penetratesthrough the source region SR and reaches the channel region CH. Thecontact hole C2 is formed simultaneously with the contact hole C1 sothat the surface of the epitaxial layer epi2 is etched also in the SBDformation region.

As a result, in the SBD formation region, phosphorus or the likesegregated on the surface of the epitaxial layer epi2 due to heattreatment can be removed. When the epitaxial layer epi2 is not opened toa predetermined depth by the contact hole C2, a Schottky junction isformed in a region of the epitaxial layer epi2 where phosphorus has beensegregated. In this case, due to the phosphorus thus segregated, thedoping concentration of the semiconductor layer forming a Schottkyjunction becomes high. This inconveniently leads to a reduction in theavalanche breakdown voltage of the Schottky barrier diode SBD. Byremoving the region of the epitaxial layer epi2 where phosphorus hasbeen segregated by forming the contact hole C2, reduction in theavalanche breakdown voltage of the Schottky barrier diode SBD can besuppressed.

As illustrated in FIG. 42, a resist film R3 is formed over theinterlayer insulating film IL in which the contact hole C1 and thecontact hole C2 have been formed. The resulting resist film R3 issubjected to exposure/development treatment to pattern the resist filmR3. The pattering of the resist film R3 is performed by exposing thepower MISFET formation region while covering the SBD formation regionwith the resist film R3.

By ion implantation with the patterned resist film R3 as a mask, p typeimpurities are introduced into the channel region CH exposed from thebottom portion of the contact hole C1. As a result, in the channelregion CH at the bottom of the contact hole C1 in the power MISFETformation region, a body contact region BC which is a p typesemiconductor region and a first semiconductor region P1 lyingtherebelow are formed. At this time, the doping concentration of thebody contact region BC is higher than the doping concentration of thefirst semiconductor region P1.

As illustrated in FIG. 43, after removal of the patterned resist filmR3, the multilayer substrate is subjected to sputter pre-cleaning. Bythis treatment, the surface of the interlayer insulating film IL isetched and the opening diameter of each of the contact hole C1 and thecontact hole C2 formed in the interlayer insulating film IL isincreased. As a result, the area of the source region SR exposed fromthe contact hole C1 can be increased.

As illustrated in FIG. 44, a titanium tungsten film 5 a is then formedover the interlayer insulating film IL having therein the contact holeC1 and the contact hole C2, followed by the formation of an aluminumfilm 5 b over the titanium tungsten film 5 a. The titanium tungsten film5 a can be formed, for example, by using sputtering and it functions asa barrier conductor film. The barrier conductor film is a film forpreventing diffusion of, for example, aluminum configuring the aluminumfilm into silicon. It is a film having a so-called barrier property. Thealuminum film 5 b is formed over the titanium tungsten film 5 a, wherebya first metal film 6 composed of the titanium tungsten film 5 a and thealuminum film 5 b can be formed.

In the power MISFET formation region, the first metal film 6 iselectrically coupled to the source region SR and the body contact regionBC and therefore functions as a source electrode. In the SBD formationregion, on the other hand, since the titanium tungsten film 5 aconfiguring the first metal film 6 is brought into direct contact withthe epitaxial layer epi2, a Schottky junction is formed. This suggeststhat the first metal film 6 including the titanium tungsten film 5 afunctions as an anode electrode of the Schottky barrier diode in the SBDformation region.

As illustrated in FIG. 6, after grinding the back side of thesemiconductor substrate 1S, a second metal film 7 is formed over theback side of the resulting semiconductor substrate 1S. The second metalfilm 7 is made of, for example, a gold film and it functions as a drainelectrode in the power MISFET formation region, while functions as acathode electrode in the SBD formation region. In such a manner, thesemiconductor device according to Embodiment 1 can be manufactured.

In Embodiment 1, the epitaxial layer formed over the semiconductorsubstrate 1S is composed of two layers, that is, the epitaxial layerepi1 having a high doping concentration and the epitaxial layer epi2having a low doping concentration. The boundary between the epitaxiallayer epi1 and the epitaxial layer epi2 is formed in a region as deep asthe bottom portion of the trench T or shallower than the bottom portionof the trench T. Embodiment 1 is therefore remarkably effective forsimultaneously realizing reduction of the on-resistance of the powerMISFET and improvement in the avalanche breakdown voltage of theSchottky barrier diode SBD which are in a trade-off relationship.

Embodiment 2

In Embodiment 2, a p ring (well layer) formed in end portions of aSchottky barrier diode SBD will be described. FIG. 45 is across-sectional view illustrating a semiconductor device according toEmbodiment 2. It has a similar configuration to that of thesemiconductor device of Embodiment 1 illustrated in FIG. 6 except thatthe width of the p ring is shown because attention is paid to the p ringPR in this Embodiment.

As illustrated in FIG. 45, also in Embodiment 2, a power MISFET and aSchottky barrier diode SBD are formed over the same semiconductorsubstrate 1S. The Schottky barrier diode SBD has a Schottky junctionobtained by bringing an epitaxial layer epi2 having a low dopingconcentration into direct contact with a titanium tungsten film 5 aconfiguring a first metal film 6. The Schottky barrier diode SBD isformed in a Schottky barrier diode SBD formation region. The p ring PRis formed in the end portions of the Schottky barrier diode SBDformation region so as to surround the Schottky barrier diode SBD withthe p ring.

The p ring PR is arranged in such a manner because of the followingreasons. For example, when the p ring PR is not formed, the epitaxiallayer epi2 which is an n type semiconductor region is brought intodirect contact with the trench T in the Schottky barrier diode SBDformation region. In this case, by a reverse bias voltage applied to theSchottky barrier diode SBD, a depletion layer extends in the endportions of the Schottky barrier diode SBD and a leakage-currentincreasing phenomenon occurs.

The end portions of the Schottky barrier diode SBD is thereforesurrounded by the p ring PR which is a p type semiconductor region.Formation of this p ring PR enables to reduce the leakage current in theSchottky barrier diode SBD because when a reverse bias voltage isapplied to the Schottky barrier diode SBD, the end portions of theSchottky barrier diode SBD can be covered with a depletion-free neutralregion. In other words, the p ring PR which is a p type semiconductorregion has a function of reducing a leakage current which occurs in theend portions of the Schottky barrier diode SBD when a reverse biasvoltage is applied to the Schottky barrier diode SBD.

A decrease in the width of the p ring PR however leads to an increase inthe leakage current of the Schottky barrier diode SBD. The p ring PR istherefore required to have an appropriate p ring width. Describedspecifically, FIG. 46 is a graph showing the relationship between areverse bias voltage VR to be applied to the Schottky barrier diode SBDand a leakage current IR flowing through the Schottky barrier diode SBD.In FIG. 46, the reverse bias voltage is plotted on the abscissa, whilethe leakage current is plotted on the ordinate. FIG. 46 shows therelationship between a reverse bias voltage and a leakage current whenthe p ring has a width of 0.15 μm, 0.25 μm, 0.35 μm, 0.45 μm and 0.55μm.

It is apparent from FIG. 46 that when the width of the p ring is 0.35 μmor greater, the leakage current is 1.0E−04A or less even if the reversebias voltage increases to 30V; and that when the width of the p ring is0.35 μm or less, the leakage current increases. From the viewpoint ofreducing a leakage current of the Schottky barrier diode SBD, it istherefore preferred to adjust the width of the p ring PR to 0.35 μm orgreater.

The p ring described in Embodiment 2 is formed when the channel regionCH of the power MISFET is formed. In other words, the p ring PR and thechannel region CH are formed in one step. The channel region CH and thep ring PR have the same doping concentration. In the channel region CH,the concentration of impurities to be introduced therein is adjusted soas to form an inversion layer when a predetermined voltage equal to orhigher than the threshold voltage is applied to a gate electrode G. Thep ring PR having the same doping concentration as that of the channelregion CH therefore does not have a doping concentration optimum forreducing the leakage current.

In view of this, the p ring PR can also be formed not in a similar stepto that of the channel region CH but in a step different therefrom. Inthis case, the concentration of impurities to be introduced into the pring PR can be set at a concentration capable of effectively reducing aleakage current. For example, it is possible to make the concentrationof impurities to be introduced into the p ring PR higher than theconcentration of impurities introduced into the channel region CH or tomake the depth of the p ring PR greater than that of the channel regionCH. Thus, when the doping concentration or depth of the p ring is setdifferent from that of the channel region CH from the standpoint ofreducing a leakage current, narrowing of the width of the p ringcompared with that when the p ring PR and the channel region CH areformed in one step is also effective for reducing the leakage currentsufficiently.

Moreover, the p ring PR preferably has a similar structure to that ofthe body structure of the power MISFET in order to satisfactorilyprevent the avalanche breakdown of the Schottky barrier diode SBD. FIG.47 is a cross-sectional view illustrating the p ring PR having a similarstructure to the body structure of the power MISFET. As illustrated inFIG. 47, the p ring PR has a second semiconductor region P2 and a thirdsemiconductor region P3, which are p type semiconductor regions. Thesecond semiconductor region P2 has a similar structure (dopingconcentration and depth) to that of the body contact region BC of thepower MISFET formation region and this region and the body contactregion BC are formed in one step. Similarly, the third semiconductorregion P3 has a similar structure (doping concentration and depth) tothe first semiconductor region P1 of the power MISFET formation regionand this third semiconductor region P3 and the first semiconductorregion P1 are formed in one step. Thus the p ring PR having thesemiconductor region P2 and the third semiconductor region P3 can haveimproved avalanche breakdown voltage. In particular, due to the effectof equipping the p ring PR with the second semiconductor region P2 andthe third semiconductor region P3 and the effect of placing the bodystructure of the MISFET and the structure of the p ring PR symmetricalrelative to the trench, the avalanche breakdown in the end portions ofthe Schottky barrier diode can be suppressed sufficiently.

The invention made by the present inventors has so far been describedspecifically based on embodiments. It should however be borne in mindthat the invention is not limited to or by them. It is needless to saythat various modifications or changes are possible without departingfrom the gist thereof.

The present invention can be used widely in the manufacturing industryof semiconductor devices.

1. A semiconductor device including a first region having a Schottkybarrier diode formed therein and a second region having a power MISFETformed therein, the first region comprising: (a1) a semiconductorsubstrate of a first conductivity type having an upper surface and alower surface on a side opposite to the upper surface; (a2) a firstsemiconductor layer of the first conductivity type formed over the uppersurface of the semiconductor substrate; (a3) a second semiconductorlayer of the first conductivity type formed over the first semiconductorlayer; (a4) a first metal film formed over the second semiconductorlayer, the first metal film and the second semiconductor layer forming aSchottky junction; and (a5) a second metal film formed over the lowersurface of the semiconductor substrate, the second region comprising:(b1) the semiconductor substrate; (b2) the first semiconductor layerformed over the semiconductor substrate; (b3) a channel region formed inthe first semiconductor layer and having a second conductivity typeopposite to the first conductivity type; (b4) a trench penetratingthrough the channel region and reaching the first semiconductor layer;(b5) a gate insulating film formed over an inner wall of the trench;(b6) a gate electrode formed over the gate insulating film and filled inthe trench; (b7) a source region of the first conductivity typecontiguous to the trench and formed over the channel region; (b8) thefirst metal film formed over the source region and electrically coupledto the source region; and (b9) the second metal film formed over thelower surface of the semiconductor substrate, wherein the first metalfilm functions as an anode electrode of the Schottky barrier diode inthe first region and as a source electrode of the power MISFET in thesecond region, wherein the second metal film functions as a cathodeelectrode of the Schottky barrier diode in the first region and as adrain electrode of the power MISFET in the second region, wherein thesecond semiconductor layer has a doping concentration lower than that ofthe first semiconductor layer, and wherein a boundary between the firstsemiconductor layer and the second semiconductor layer is formed in aregion as deep as the bottom portion of the trench or in a regionshallower than the bottom portion of the trench, and wherein the secondregion further comprises: (b10) a contact hole arranged apart from thetrench and having a depth greater than that of the source region; (b11)a body contact region formed below the bottom portion of the contacthole and comprising a semiconductor region of the second conductivitytype; and (b12) a first semiconductor region contiguous to the bodycontact region and comprising a semiconductor region of the secondconductivity type formed in a region deeper than the body contactregion, and wherein the contact hole is filled with the first metalfilm.
 2. The semiconductor device according to claim 1, wherein thedoping concentration of the second semiconductor layer becomes higherwith the depth from the surface of the second semiconductor layer inwhich the Schottky junction has been formed.
 3. The semiconductor deviceaccording to claim 2, wherein the doping concentration in the surface ofthe second semiconductor layer in which the Schottky junction has beenformed is 8.0×10¹⁵/cm³ or less.
 4. The semiconductor device according toclaim 1, wherein the doping concentration of the second semiconductorlayer is constant from the surface of the second semiconductor layerwhere the Schottky junction has been formed to a predetermined depth,and the doping concentration increases as the depth becomes greater thanthe predetermined depth.
 5. The semiconductor device according to claim4, wherein the doping concentration of the second semiconductor layerfrom the surface to the predetermined depth is 8.0×10¹⁵/cm³ or less. 6.The semiconductor device according to claim 1, wherein the dopingconcentration of the first semiconductor layer increases from theboundary between the first semiconductor layer and the secondsemiconductor layer toward the boundary between the first semiconductorlayer and the semiconductor substrate.
 7. The semiconductor deviceaccording to claim 1, wherein the first semiconductor layer and thesecond semiconductor layer are epitaxial layers.
 8. The semiconductordevice according to claim 1, wherein the first metal film comprises abarrier conductor film and a metal film formed over the barrierconductor film.
 9. The semiconductor device according to claim 8,wherein the Schottky junction of the Schottky barrier diode is formed bya contact between the second semiconductor layer and the barrierconductor film.
 10. The semiconductor device according to claim 9,wherein the barrier conductor film is a titanium tungsten film.
 11. Thesemiconductor device according to claim 9, wherein the barrier conductorfilm is a titanium nitride/titanium film stack.
 12. The semiconductordevice according to claim 9, wherein the barrier conductor film is acobalt film.
 13. The semiconductor device according to claim 8, whereinthe metal film is an aluminum film.
 14. The semiconductor deviceaccording to claim 1, wherein the Schottky barrier diode and the powerMISFET are parts of a plurality of elements configuring a DC/DCconverter for converting a voltage value of a DC current voltage. 15.The semiconductor device according to claim 14, wherein the power MISFETis a synchronous rectification power MISFET configuring the DC/DCconverter, and wherein the Schottky barrier diode is coupled in parallelto the power MISFET.
 16. The semiconductor device according to claim 1,wherein the doping concentration of the body contact region is higherthan the doping concentration of the first semiconductor region.
 17. Thesemiconductor device according to claim 16, wherein the first region issandwiched between the second regions, and wherein the first region has,at both ends thereof, well layers comprising a semiconductor layer ofthe second conductivity type so as to sandwich the Schottky barrierdiode formed in the first region between the well layers, and whereinthe doping concentration of the well layers is different from the dopingconcentration of the channel region formed in the second region.
 18. Thesemiconductor device according to claim 17, wherein the first regionfurther comprises: (a6) a second semiconductor region of the secondconductivity type which is contiguous to the first metal film andarranged in the well layer; and (a7) a third semiconductor layer of thesecond conductivity type which is contiguous to the second semiconductorregion and formed in a region deeper than the second semiconductorregion, wherein the second semiconductor region formed in the firstregion has a similar structure to that of the body contact region formedin the second region, and wherein the third semiconductor region formedin the first region has a similar structure to that of the firstsemiconductor region formed in the second region.
 19. A manufacturingmethod of a semiconductor device, comprising the steps of: (a) preparinga multilayer substrate having a semiconductor substrate of a firstconductivity type, a first semiconductor layer of the first conductivitytype formed over the semiconductor substrate, and a second semiconductorlayer of the first conductivity type formed over the first semiconductorlayer and having a doping concentration lower than that of the firstsemiconductor layer; (b) forming a trench in a second region of themultilayer substrate in which a power MISFET is to be formed; (c)forming a gate insulating film over an inner wall of the trench; (d)forming a gate electrode over the gate insulating film so as to fill thetrench with the gate electrode; (e) forming a channel region of a secondconductivity type opposite to the first conductivity type in the secondregion of the multilayer substrate; (f) forming, in the second region ofthe multilayer substrate, a source region contiguous to the trench andcomprising a semiconductor region of the first conductivity type; (g)forming a contact hole in the second region of the multilayer substrate,wherein the contact hole is arranged apart from the trench and has adepth greater than that of the source region; (h) forming a body contactregion of the second conductivity type under a bottom portion of thecontact hole; (i) forming a first semiconductor region of the secondconductivity type under the body contact region, wherein the firstsemiconductor region is contiguous to the body contact region; (j)forming a first metal film which is contiguous to the source region andthe body contact region in the second region of the multilayer substrateand which is contiguous to the second semiconductor layer to form aSchottky junction in a first region of the multilayer substrate in whicha Schottky barrier diode is to be formed; and (k) forming a second metalfilm over a lower surface of the semiconductor substrate included in themultilayer substrate, wherein the first metal film serves as a sourceelectrode of the power MISFET in the second region and serves as ananode electrode of the Schottky barrier diode in the first region,wherein the second metal film serves as a drain electrode of the powerMISFET in the second region and serves as a cathode electrode of theSchottky barrier diode in the first region, and wherein, aftercompletion of the power MISFET and the Schottky barrier diode, aboundary between the first semiconductor layer and the secondsemiconductor layer is present in a region as deep as or shallower thanthe bottom portion of the trench.
 20. The manufacturing method of asemiconductor device according to claim 19, wherein the secondsemiconductor layer after completion of the power MISFET and theSchottky barrier diode includes a residual region having a dopingconcentration equal to that of the second semiconductor layer during thestep (a).
 21. The manufacturing method of a semiconductor deviceaccording to claim 20, wherein the steps until the completion of thepower MISFET and the Schottky barrier diode comprise a step of heattreating the multilayer substrate.
 22. The manufacturing method of asemiconductor device according to claim 21, wherein the heat treatmentstep decreases the thickness of the second semiconductor layer.
 23. Themanufacturing method of a semiconductor device according to claim 21,wherein the boundary between the second semiconductor layer and thefirst semiconductor layer becomes shallower by the heat treatment step.24. The manufacturing method of a semiconductor device according toclaim 23, wherein the doping concentration of the first semiconductorlayer increases from a shallow region in which the upper surface of thefirst semiconductor layer has been formed toward a deep region in whichthe lower surface of the first semiconductor layer has been formed.